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| 1 uAE*OA 1/2e EU S3C44B0X 16/32 I RISC |AiAE/Ee1/4IEOEIa(c)OoI3/4OAU*1/2 EyCA S3C44B0XIa(c)OOIAAaOA2.5V ARM7TDMI AUEoO 8Kcache ;ENAinternal SRAM;LCD Controller(xioO256ESTN EOALCD xOADMA) 2-ch UART with handshake(IrDA1.0, 16-byte FIFO) / 1-ch SIO 2-ch general DMAs / 2-ch peripher al DMAs with external request pins External memory controller (chip select logic, FP/ EDO/SDRAM controller) 5-ch PWM timers & 1-ch internal timerWatch Dog Timer 71 general purpose I/O ports / 8-ch external interrupt source RTC with calendar function 8-ch 10-bit ADC 1-ch multi-master IIC-BUS controller 1-ch IIS-BUS controller Sync. SIO interface and On-chip clock generator with PLL. S3C44B0XEOAOOAAEyCARM CPU CEexUI1/2a-SAMBA2 xioi66MHZ cOUAiO Normal, Slow, Idle, and Stop mode IIUAi|A 1 Little/Big endian support. 2 Address space: 32Mbytes per each bank. (Total 256Mbyte) 3 Supports programmable 8/16/32-bit data bus width for each bank. 4 Fixed bank start address and programmable bank size for 7 banks. 5 . 8 memory banks. - 6 memory banks for ROM, SRAM etc. - 2 memory banks for ROM/SRAM/DRAM(Fast Page, EDO, and Synchronous DRAM) 6. Fully Programmable access cycles for all memory banks. 7 Supports external wait signal to expend the bus cycle. 8. Supports self-refresh mode in DRAM/SDRAM for power-down. 9. Supports asymmetric/symmetric address of DRAM. Cache IAUaeAE/|U: * 4-way set associative ID(Unified)-cache with 8Kbyte. * The 0/4/8 Kbytes internal SRAM using unused cache memory. * Pseudo LRU(Least Recently Used) Replace Algorithm. * Write through policy to maintain the coherence between main memory and cache content. * Write buffer with four depth. * Request data first fill technique when cache miss occurs. EOOIcOUAi * Low power * The on-chip PLL makes the clock for operating MCU at maximum 66MHz. * Clock can be fed selectively to each function block by software. * Power mode: Normal, Slow, Idle and Stop mode. Normal mode: Normal operating mode. Slow mode: Low frequency clock without PLL Idle mode: Stop the clock for only CPU Stop mode: All clocks are stopped * Wake up by EINT[7:0] or RTC alarm interrupt from idle mode. * 30 Interrupt sources( Watch-dog timer, 6 Timer, 6 UART, 8 External interrupts, 4 DMA , 2 RTC, 1 ADC, 1 IIC, 1 SIO ) * Vectored IRQ interrupt mode to reduce interrupt * Programmable polarity of edge and level * Supports FIQ (Fast Interrupt request) for very urgent interrupt request latency. * Level/edge mode on the external interrupt sources EAE/|AU * 5-ch 16-bit Timer with PWM / 1-ch 16-bit internal timer with DMA-based or interrupt-based operation * Programmable duty cycle, frequency, and polarity * Dead-zone generation. * Supports external clock source. RTC |AU: * Full clock feature: msec, sec, min, hour, day,week, month, year. * 32.768 KHz operation. * Alarm interrupt for CPU wake-up. * Time tick interrupt IOAEaEe oU|AU: * 8 external interrupt ports * 71 multiplexed input/output ports UART |AU: * 2-channel UART with DMA-based or interrupt-based operation * Supports 5-bit, 6-bit, 7-bit, or 8-bit serial data transmit/receive * Supports H/W handshaking during transmit/receive * Programmable baud rate * Supports IrDA 1.0 (115.2kbps) * Loop back mode for testing * Each channel have two internal 32-byte FIFO for Rx and Tx. DMAOOAE/|AU: * 2 channel general purpose Direct Memory Access controller without CPU intervention. * 2 channel Bridge DMA (peripheral DMA) controller. * Support IO to memory, memory to IO, IO to IO with the Bridge DMA which has 6 type's DMA requestor: Software, 4 internal function blocks (UART, SIO, Timer, IIS), and External pins. * Programmable priority order between DMAs (fixed or round-robin mode) * Burst transfer mode to enhance the transfer rate on the FPDRAM, EDODRAM and SDRAM. * Supports fly-by mode on the memory to external device and external device to memory t ransfer mode A/D xAE/: * 8-ch multiplexed ADC. * Max. 100KSPS/10-bit. LCDOOAE/: * Supports color/monochrome/gray LCD panel * Supports single scan and dual scan displays * Supports virtual screen function * System memory is used as display memory * Dedicated DMA for fetching image data from system memory * Programmable screen size * Gray level: 16 gray levels * 256 Color levels AA*EAE/: * 16-bit Watchdog Timer * Interrupt request or system reset at time-out IIC-BUS 1/2OU * 1-ch Multi-Master IIC-Bus with interrupt-based operation. * Serial, 8-bit oriented, bi-directional data transfers can be made at up to 100 Kbit/s in the standard mode or up to 400 Kbit/s in the fast mode. IIS-BUS1/2OU * 1-ch IIS-bus for audio interface with DMA-based operation. * Serial, 8/16bit per channel data transfers * Supports MSB-justified data format SIO (I1/2(R)U): * 1-ch SIO with DMA-based or interrupt -based operation. * Programmable baud rates. * Supports serial data transmit/receive operations 8-bit in SIO. Ux/cN*I: * : 2.5V I/OcN : 3.0 V to 3.6 V x/AEAE: * Up to 66 MHz *ax: * 160 LQFP / 160 FBGA 2 1/4aOEOa(c)U1/2AAIA-AcxeE*. U1/2AAeEo EeOAS3C44B0X OUaEA1/2IE*nGCS0AxUIiE, A1/4-cAE1/2OUI 00:8-bit 01:16-bit 10:32-bit 11:Test mode om[1:0]: EaEe om[1:0] ADDR[24:0] Eao: DATA[31:0] EaEeo: nGCS[7:0] Eao: I. nWE Eao : nBE[3:0] Eao: nOEEao : AOEiA, OEiA, xO1/2UOEiA 3/4AENOn, OO*xUI Ey3/4YxUI, aeAE/OO*OUIaO|IACooE1/4i. OE3/4CAxUIAEUI. OUEOASRAM OE3/4CAxUIAEUIA. CeoIAxO1/2UOEiA. EaoIaO|IAaeAE/OO*. xUIiEEaII8/16/32 I aeEOUAEUIIcEa nWBE[3:0] Eao: nXBREQ EaEe: nXBREQ nXBACKA1/4iOE3/4ON-A1/2xUIOAEE nXBACK EaoxUIO|A nWAIT nWAITCOOIUAEUAxNOCoe EaEe ENDIAN 3/4YAaIEClEyEuE* eEaittle endian EIA-AcxeE*. xUIOOAECeoAOEiAOo/3/4 nWAITIEAEUAUIeIOCx EC big endianAU1/2AAEU1/4aOEAI-cOA 0:little endian 1:big endian nRAS[1:0] EaoOO*NIA nCAS[3:0] Eao nSRASEaoSDRAM nSCASEaoSDRAM nSCS[1:0] EaoSDRAM DQM[3:0] EaoSDRAM SCLKEaoSDRAM SCKEEaoSDRAM VD[7:0]Eao IAOE3/4CoyY VFRAMEEaoLCD VMEaoVM Ao VLINEEaoLCD VCLKEaoLCD TOUT[4:0]EaoEAE/A TCLKEaEeIaEOOA EINT[7:0]EaEeIaOICoA nXDREQ[1:0]EaEeIaDMA nXDACK[1:0]EaoIaDMA RxD[1:0]EaEeUART TxD[1:0]EaoUART nCTS[1:0]EaEeUART nRTS[1:0]EaoUART IICSDAEaEeEoIIC IICSCLEaEeEoIIC IISLRCKEaEeEoIISxUIIAEOONOnA IISDOEaoIISxUI(R)Ey3/4YaoA IISDIEaEeIISxUI(R)Ey3/4YaEeA IISCLKEaEeEoIISxUI(R)EOO CODECLKEaoCODEC SIORXDEaEeSIO SIOTXDEaoSIO SIOCKEaEeEoSIO SIORDYEaEeEoSIO AIN[7:0] ADC AREFTEaEeADC AaAEaEe I1/4cNEaEe *EIEy3/4YI EOOA ADMA IeESIO Ux/EAIOOA 1/2OEOy3/4YaEeI IIEOO xUIEOO xUIEy3/4Y Ceo*EIEaoA *EIEy3/4YI Cay*EIEaEeA 1/2OEOy3/4YaEeI O|A CeoA AOUOEy3/4YxoAE1/2oLCD aEOOAy3/4YOUVCLK AEIyNO*EIOUA1/2LCD CyAE/oO CyAE/ENu 1/4OaALCD AOE3/4OA1/4OUO EAecNA1/4OOOoaIUoVLINE LCDEyUCOYI3/4 EOOA EOOOiA 4IEEAeA LCDE VD[3:0]IEy3/4YCoEIO VD[7:4]I Ey3/4YAEAIA AOO*NIA OO*NIA AOO*NIA 3/4AENOnA AREFBEaEeADC AVCOMEaEeADC P[70:0]EaEeEoIOAI/O nRESETIA nRESETOeOIcAE1/2AEU4 OM[3:2]EaEeOM[3:2] xI1/4cNEaEe I1/4cNEaEe UO(c)OOEaoA1/2 nRESET*AS3C44B0X OAEIo oMCLK OUAEU E*EOOA1/2 EON3/4-IEOoIUcx1/2o 00 = Crystal(XTAL0,EXTAL0), PLL on 01 = EXTCLK, PLL on 10, 11 = Chip test mode. EXTCLKEaEeOM[3:2] XTAL0AAaEaEeIIOOUOnA*3/4Ia1/2AAO3.3V EXTAL0A1/2EuECXTAL0 AaoA*A3/4IaIOOUOnIE aoAa OeuO PLLCAPAAaEaEe1/2OIIO*AEcY700PF XTAL1AAaEaEeRTC EXTAL1AAaEaoRTC CLKoutEaoEOOA nTRSTEaEeTAP OeA1/2OOo10K TMSEaEe TCKEaEeTAP TDIEaEeTAP cxe TDOEaoTAP OOAE/Ey3/4YaoACaOAiIA(R)1/2 (c) VDD S3C44B0X AUEA1/4-cN2.5V VSS: S3C44B0XAUEA1/4-O. VDDIO: S3C44B0X I/OUcO(3.3V). VSSIO: S3C44B0X I/OO. RTCVDD:RTCcN(2.5V VDDADC:ADCcN(2.5V). VSSADC:ADCO. o3V, O3.3V). TAPNOnAE1/2OOAE/A OOAE/EOAIa(c)JTAG OOAE/Ey3/4YaEeACaOAiIA(R)1/2OOo10K OOAE/IAnTRSTOUTAP EIA-cxe*nOonTRSTOeIIcAE1/2 AEOO TAPoAxIIOOAE/ OoOeA1/2O A1/4-AEOOAOOeA1/2Oo10K 10KEexc-IA EIA-cxe EIAAEoEITAP OOAE/EoEOAdebugger EOOA3/4IaaEe1/2A EOOA3/4Iaao1/2AEuCXTAL1 A*xEaoA (c) OAE AxaoA* NOnIaEOOAaEeAIAO1/23.3V (c). (c). 3 OAi1/4 4 ae UAi 1 BWSCON 0x01C80000 IAuAE BIT ST7 31 |AU AIE*BANK7 0- EOA 1- EOA WS7 DW7 ST6 30 [29:28] 27 AIE*BANK7 AA1/2IE*BANK7 AIE*BANK6 EIASRAM PIN[14:11] PIN[14:11] EIASRAM AEy3/4YxUIOiE EIASRAM EC*nOAUB/LB EC*nOAUB/LB x/I nWBE[3:0] x/I nBE[3:0] aeAE/AEyxI (c) (c) R/W xUIiEOeyIOOAE1/4Aae/ oE1/4OI0 0- WAIT disable 1 = WAIT enable 00 = 8-bit 01 = 16-bit, 10 = 32-bit 2- EOA 3- EOA WS6 DW6 ST5 26 [25:24] 23 AIE*BANK6 AA1/2IE*BANK6 AIE*BANK5 4- EOA 5- EOA WS5 DW5 ST4 22 [21:20] 19 AIE*BANK5 AA1/2IE*BANK5 AIE*BANK4 6- EOA 7- EOA WS4 DW4 ST3 18 [17:16] 15 AIE*BANK4 AA1/2IE*BANK4 AIE*BANK3 8- EOA 9- EOA WS3 DW3 ST2 14 [13:12] 11 AIE*BANK3 AA1/2IE*BANK3 AIE*BANK2 10- EOA 11- EOA WS2 DW2 ST1 10 [9:8] 7 AIE*BANK2 AA1/2IE*BANK2 AIE*BANK1 12- EOA 13- EOA WS1 DW1 DW0 6 [5:4] [2:1] AIE*BANK1 AA1/2IE*BANK1 AA1/2IOE3/4BANK0 PIN[14:11] PIN[14:11] EIASRAM AEy3/4YxUIOiE EIASRAM PIN[14:11] PIN[14:11] EIAaeAE/EyxI AEy3/4YxUIOiE EIASRAM PIN[14:11] PIN[14:11] EIAaeAE/EyxI AEy3/4YxUIOiE EIASRAM PIN[14:11] PIN[14:11] EIAaeAE/EyxI AEy3/4YxUIOiE EIASRAM PIN[14:11] PIN[14:11] EIAaeAE/EyxI AEy3/4YxUIOiE EIASRAM PIN[14:11] PIN[14:11] EIAaeAE/EyxI AEy3/4YxUIOiE x/I nWBE[3:0] x/I nBE[3:0] aeAE/AEyxI (c) (c) 0- WAIT disable 1 = WAIT enable 00 = 8-bit 01 = 16-bit, 10 = 32-bit EC*nOAUB/LB x/I nWBE[3:0] x/I nBE[3:0] (c) (c) 0- WAIT disable 1 = WAIT enable 00 = 8-bit 01 = 16-bit, 10 = 32-bit EC*nOAUB/LB x/I nWBE[3:0] x/I nBE[3:0] (c) (c) 0- WAIT disable 1 = WAIT enable 00 = 8-bit 01 = 16-bit, 10 = 32-bit EC*nOAUB/LB x/I nWBE[3:0] x/I nBE[3:0] (c) (c) 0- WAIT disable 1 = WAIT enable 00 = 8-bit 01 = 16-bit, 10 = 32-bit EC*nOAUB/LB x/I nWBE[3:0] x/I nBE[3:0] (c) (c) 0- WAIT disable 1 = WAIT enable 00 = 8-bit 01 = 16-bit, 10 = 32-bit EC*nOAUB/LB x/I nWBE[3:0] x/I nBE[3:0] (c) (c) 0- WAIT disable 1 = WAIT enable 00 = 8-bit 01 = 16-bit, 10 = 32-bit AEy3/4YxUIOiE(ONLY READ,OEOM[1:0] xIOEENDIAN pins E*) 1/2AE*) 00 = 8-bit 01 = 16-bit, 10 = 32-bit ENDIAN 0 AIOE3/4endian mode (read only 0 = Little endian 1 = Big endian 2 BANKCON0 BANKCON1 BANKCON2 BANKCON3 BANKCON4 IAuAE BIT Tacs [14:13] 0x01C80004 0x01C80008 0x01C8000C 0x01C80010 0x01C80014 |AU OUnGCSn 01 = 1 clock 11 = 4 clocks OUnOE EI3/4AENOn1/2AE1/4a 01 = 1 clock 11 = 4 clocks aeEOUAEU 001 = 2 clocks 011 = 4 clocks 101 = 8 clocks 111 = 14 clocks OUnOE EI3/4AENOnOE1/4a 01 = 1 clock 11 = 4 clocks OUnGCSnOOO*E1/4a 01 = 1 clock 11 = 4 clocks OAE1/2aeEOUAEU 01 = 3 clocks 11 = 6 clocks OAE1/2AaOA 01 = 4 data 11 = 16 data OO* BANKCON6 BANKCON7 IAuAE MT BIT [16:15] 0x01C8001C 0x01C80020 |AU OaA1/2IE*bank6 I bank7aeAE/AaI 01 = FP DRAM 11 = Sync. DRAM AaI OUnGCSn 01 = 1 clock 11 = 4 clocks OUnOE EI3/4AENOn1/2AE1/4a OO(R)CO*1/2AE1/4a R/W R/W AeEo Bank 6 control register Bank 7 control register oE1/4O 0x18008 0x18008 OO(R)CO*1/2AE1/4a R/W R/W R/W R/W R/W R/W Bank 0 control register Bank 1 control register Bank 2 control register Bank 3 control register Bank 4 control register Bank 5 control register 0x0700 0x0700 0x0700 0x0700 0x0700 0x0700 BANKCON5 0x01C80018 00 = 0 clock 10 = 2 clocks Tcos [12:11] 00 = 0 clock 10 = 2 clocks Tacc [10:8] 000 = 1 clock 010 = 3 clocks 100 = 6 clocks 110 = 10 clocks Toch [7:6] 00 = 0 clock 10 = 2 clocks Tcah [5:4] 00 = 0 clock 10 = 2 clocks Tpac [3:2] 00 = 2 clocks 10 = 4 clocks PMC [1:0] 00 = normal (1 data) 10 = 8 data 1/4AaeAE/Au 00 = ROM or SRAM 10 = EDO DRAM OOUROM Tacs ISRAM [14:13] 00 = 0 clock 10 = 2 clocks Tcos [12:11] 00 = 0 clock Tacc [10:8] 01 = 1 clock aeEOUAEU 001 = 2 clocks 011 = 4 clocks 101 = 8 clocks 111 = 14 clocks OUnOE EI3/4AENOnOE1/4a 10 = 2 clocks 11 = 4 clocks 000 = 1 clock 010 = 3 clocks 100 = 6 clocks 110 = 10 clocks Toch [7:6] 00 = 0 clock 01 = 1 clock 10 = 2 clocks 11 = 4 clocks Tcah [5:4] OUnGCSnOEOO*1/4a 01 = 1clock 11 = 4 clocks 00 = 0 clock 10 = 2 clocks Tpac [3:2] OAE1/2aeEOUAEU 00 = 2 clocks 01 = 3 clocks 10 = 4 clocks 11 = 6 clocks PMC [1:0] OAE1/2AaOA 01 = 4 consecutive accesses 11 = 16 consecutive accesses NOEy 00 = normal (1 data) OOUFP DRAMI Trcd [5:4] 00 = 1 clock 10 = 3 clocks Tcas Tcp CAN [3] [2] [1:0] AOO*EyA 01 = 9-bit 11 = 11-bit AaI RAS 1/2 CAS AOO*EyA 01 = 9-bit DRAM SROM SDRAM SROM DRAM SDRAM 10= 10-bit NOE 0 = 1 clock 0 = 1 clock 00 = 8-bit 10 = 10-bit OOUSDRAM Trcd [3:2] SCAN [1:0] 00 = 8-bit SROM SDRAM SROM DRAM OAxeI SDRAM DRAM 3 10 = 8 consecutive accesses EDO DRAMAaI RAS 1/2 CAS 01 = 2 clocks 11 = 4 clocks CAS AoaiE 1 = 2 clocks CAS OacOUAEU 1 = 2 clocks 00 = 2 clocks 01 = 3 clocks 10 = 4 clocks BANK7 BANK6 OAaeAE/AaIxeI REFRESH IAuAE REFEN TREFMD OUself-refresh Trp DRAM : 0x01C80024 BIT [23] [22] R/W |AU DRAM/SDRAMEAOOAE1/4Aae/ oE1/4O0xac0000 DRAM/SDRAMEAOEi DRAM/SDRAMEAAE1/2 OOAEAEc1/2Cy DRAM/SDRAM RAS OacE1/4 0 = Disable 1 = Enable (self or CBR/auto refresh) 0 = CBR/Auto Refresh 1 = Self Refresh E, DRAM/SDRAM [21:20] 00 = 1.5 clocks 01 = 2.5 clocks 10 = 3.5 clocks 11 = 4.5 clocks SDRAM : 00 = 2 clocks 01 = 3 clocks 10 = 4 clocks 11 = Not support Trc Tchr Reserved Refresh Counter EAOUAEU1/4aE1/2: Refresh period = (2^ 11 -refresh_count+1)/MCLK EcuEAOUAEUEC15.6 us refresh countEcIA1/4AEEa refresh count = 2 ^11 + 1 - 60x15.6 = 1113 4 BANKSIZE IAuAE BIT SCLKEN 0 = normal Reserved BK76MAP 110 = 8M/8M 4 SDRAMAE1/2EeOA1/4AaeAE/ 0x01C8002C 0x01C80030 |AU [9] [8:7] aEOA1/2 I*AoaE R/W R/W bank6AE1/2EeOA1/4AaeAE/ oE1/4O xxx bank7AE1/2EeOA1/4AaeAE/ oE1/4O xxx MRSRB6 MRSRB7 IAuAE WBL 0ECIAE1/4oO TM 00: aEOA1/2 01, 10, 11: Ao CL [6:4] CAS I*IiO|E1/4a 000 = 1 clock, 010 = 2 clocks, 011=3 clocks BIT [4] SCLK =1 [3] [ 2:0] AoI0 BANK6/7aeAE/OEa 101 = 4M/4M EeOAI1 E|A1/4oEUIAEoeOAI 1 0x01C80028 |AU OoSCLK 1/2oOUSDRAM aeEOUAEUuEOaoIO/1/2 R/W Ic1/4AaeAE/ oE1/4OI 0x0 I MCLK EC 60 MHz, [19:18] [17:16] [15:11] [10:0] SDRAM RAS ICAS DRAMACAS OE1/4a Not use DRAM/SDRAMEA1/4AEEyO xiE1/4a 00 = 4 clocks 01 = 5 clocks 10 = 6 clocks 11 = 7 clocks 00 = 1 clock 01 = 2 clocks 10 = 3 clocks 11 = 4 clocks 000 = 32M/32M 100 = 2M/2M 111 = 16M/16M = Ao BT 0: Ao ( 1: N/A BL 000: 1 AEaEu: N/A x1 IoOUSDRAM 2 EuOAaeOOAE1/4/eEASTMIA 3 OUIOSL_IDLE DRAM/SDRAM Oe1/2oExOEAAE OEEA1/4AaeAE/OOAAa OAiEeA [2:0] I*E IAE1/4o) [3] I*Aa 5 EOOIcOUAiA 1/2 S3C44B0XAcOUAiO5 1 Normal mode, E1/2CPU OUOyA AoIaEeAEOO(c)| 2 AOAOUIaEOAEA 3 Idle mode Idle modeIOCPU CORE OoOCPU 4 AOICeoUES3C44B0X Stop mode Stop mode 1/2aEuOAEO(c)|PLL S3C44B0XAA(c)cA/EUOU10UA 5 SL Idle mode SL Idle mode yAELCD S3C44B0XAEOOOEOAIa3/4IaAu1/2aEeOOM[3:2] I3/4o. M[3:2] x: OUIoPLL EOA, OaEFOUT O1/2OEao OAE1/2 AUEOAS/W xioAOaE| x/IaEe1/4OyOAEu iIOA Slow mode Slow modeIC* PLLAE1/2 PLLOcIuUAAE1/2OOx/IIa AEUcOIu1/4oOoE EOOIaEeIa(c)1/2oOEu O|O(c)AE OAAE1/2N OIOOaEAcOIuxiEUA/1/2oC IaOIAUECPU OOAE/1/2aEuOAE xA AEIyNOOOM3 OAiEeA I OM2 aEOA1/2 AU OAAE1/2N AxIOUnRESET AEo, APLL OUOAS/W AEOOOA3/4Ia, 1/2AAcAE3/4o. M[3:2]=00 Crystal clock M[3:2]=01 Ext. Clock AEaEu Crystal clockoIaEOO. OaEEXTCLK R/W PLLOOAE1/4Aae/ PLLCONIOAO(R)C,PLL OUTPUT (FOUT) EcuS3C44B0X 1 PLLOOAE1/4Aae/ PLLCON A1/4AaeAE/EeOPLL PLLEaoAEAE1/4Ea1/2EcI: AUx/ITimer 5 AEOOOTCLK. IO 0x38080 0x01D80000 IEy. Fpllo = (m * Fin) / (p * 2s) m = (MDIV + 8), p = (PDIV + 2), s = SDIV FplloOeoOU20MHZ IEUOU66MHZ. Fpllo * 2 IAuAE s OeEUOU170MHZ ooOU AeEo OU2MHZ. AEIO Fin / pTIAE1/4oI1MHZ BIT MDIV PDIV SDIV 2 IAuAE IIS IIC ADC RTC GPIO UART1 UART0 EOOOAE1/4Aae/ CLKCON BIT [19:12] [9:4] [1:0] MDIVO PDIVO SDIVO 0x38 0x08 0x0 R/W AOOO AOOO AOOO AOOO, AOOO, AOOO AOOO AOOO, EcuBDMA OI, OUIaEexUIA 1/4EAI0,. RTC EeOAI1, OEiOAEINT[4:7] EAE/EOx AOI. EOOOAE1/4Aae/ oE1/4O 0x7ff8 0x01D80004 AeEo [14] [13] [12] [11] [10] [9] [8] OOAE IIS block OOAE IIC block OOAE ADC block OOAE RTC block OOAE GPIO block OOAE UART1 block OOAE UART0 block OOAE BDMA block aeE 0 = Disable, 1 = Enable 0 = Disable, 1 = Enable 0 = Disable, 1 = Enable 0 = Disable, 1 = Enable 0 = Disable, 1 = Enable 0 = Disable, 1 = Enable 0 = Disable, 1 = Enable BDMA0,1 [7] 0 = Disable, 1 = Enable LCDC SIO ZDMA0,1 [6] OOAE LCDC block [5] [4] OOAE SIO block OOAE ZDMA block AOOO AOOO AOOO AOOO 0 = Disable, 1 = Enable 0 = Disable, 1 = Enable 0 = Disable, 1 = Enable PWMTIMER [3] IDLE SL_IDLE [2] [1] OOAE PWMTIMER block 1/2oEe IDLE mode. AIAUxOCay AIAUxOCay. 1/4AaeAE/OeEOU 0x46. 0 = Disable, 1 = Enable 0 = Disable, 1 =1/2oEe IDLE mode 1/2oEeSL_IDLE mode option. IAE1/2oEeSL_IDLE mode, CLKCON 0 = Disable, 1 = SL_IDLE mode. STOP 3 AyEOOOAE1/4Aae/ 0x01D80008 AeEo [5] 1/2oAUOUSLOW_BIT=1 Eo, OUPLL IEo(150US), SLOW_BITIEOOCay R/W AyEOOOAE1/4Aae/ oE1/4O 0x9 IAuAE BIT PLL_OFF 0 : PLL o,. PLL [0] 1/2oEe STOP mode. AIAUxOCay. 0 = Disable 1 =1/2oEeSTOP mode CLKSLOW 1 : PLL Oo, PLL SLOW_BIT [4] 1/2oAUOUSLOW_BIT=1 EOo 0 : Fout = Fpllo (PLL output) 1: Fout = Fin / (2 x SLOW_VAL), (SLOW_VAL > 0) Fout = Fin, (SLOW_VAL =0) SLOW_VAL 4 EoE1/4aAEyOAae/ LOCKTIME 0x01D8000C R/W EoE1/4aAEyOAae/ oE1/4O 0xfff [3:0] OaEAIECOUSLOW_BIT IoEslow clock A*OAE 6 CPU WRAPPER & BUS PRIORITIES CPU WRAPPER uAOo8KBYTEcache, write buffer, 8KBYTEcacheEOOEyO*1/2EOA 1. E8K 3 E8K CacheEOA AUSRAM O/OOAA1/4oEUIIEa. AaeOEaOO* aeOEaOO* 0x10000000 - 0x100007ff 0x10000800 - 0x10000fff 0x10001000 - 0x100017ff 0x10001800 - 0x10001fff 0x10002000 - 0x100027f0 0x10002800 - 0x10002ff0 0x10003000 - 0x100037f0 0x10003800 - 0x10003ff0 0x10004000 - 0x100047f0 OUcache tagILRU OeEC0 ICPU E. x/IOAi/ x/IAUaeAEEOA. Ey3/4Ycache AiIa4K xoIcache EOAwrite-through AaOEy3/4YOO. 2. 4KxoIAUSRAM, xi1/2uEUEOAEa*AIaOA, cache set ILRU cache ILRU cache set 0 cache set 1 cache set 2 cache set 3 cache tag 0 cache tag 1 cache tag 2 cache tag 3 LRU OUcache set AOO*AoOo1/4O, xO, AOO*Oo, xIOoMAS OO*A bit[3:0] c 2KB 2KB 2KB 2KB 512bytes 512bytes 512bytes 512bytes 512bytes OAO*OO16BYTE AOo1/4O, Ey3/4YOo, AIAOo Oo28BIT . AoaCo1/4AaeAE/uAO32BIT AxIOoMAS. S3C44B0XOEAoaCo1/4aeAE/, OE3/4yYAO*,2BIT E*Ey3/4YA1/2 00 = 8-bit data mode 01 = 16-bit data mode 10 = 32-bit data mode 11 = Not used OU S3C44B0X,OAEoxUIOOe: LCD_DMA, BDMA0, BDMA1, ZDMA0, ZDMA1, I CPU wrapper. nBREQ (IaxUIOOAEe), OUIoOAIE1/41/2IcA: 1. DRAM refresh controller 2. LCD_DMA 3. ZDMA0,1 4. BDMA0,1 5. External bus master 6. Write buffer 7. Cache & CPU LCD_DMA, ZDMA, BDMA, and an external bus masterAOAIE1/4EOOIySBUSCON AE/aIAa, EOONn-*OAAIE1/4AE1/2II, e1/4OIaIAAE, CPU wrapper xUECiIAOAIE1/4, AUa OUN-*OAAIE1/4AE1/2, EuOAxUIOOAE 1/4Aae 1/4AaeAE/Oa. 1 IIAaOA1/4AaeAE/ SYSCFG IAuAE Reserved Reserved DA(reserved) 0: OEi RSE(reserved) 0: OEiAIO 1: OEiAIO WE 1/4a, EcuOEia, 0 =OEiaUx/ 1 = CM [2:1] OaA1/2IE*cache [3] AIE*aAOEi/ OUOEAoAO(R)1/4aUAE1/2Ex/Oy. OEiaUx/ AE1/2 OEi. O(c)IaxOAeiAUAEUE 0x01C00000 I [7] [6] [5] Ey3/4YOi 1: OEiy3/4YOi [4] OEiAIONIi. AEy3/4YaEeOo1/4aOUAEU IAE1/4oOI0. Ey3/4YOiOOAE, Ao Ao IAE1/4oOI0. R/W AeEo IIAaOA1/4AaeAE/ AEIO 0x01 AIONIiOUcache & CPU core 00 = Disable cache (8KB internal SRAM) 01 = Half cache enable (4KB cache, 4KB internal SRAM) 10 = Reserved 11 = Full Cache enable (8KB cache) SE 0: OEiIONIi1: 2 NON-CACHEABLECoOoOOAE1/4Aae/ NCACHBE0 NCACHBE1 IAuAE SE0 0x01C00004 R/W 0x01C00008 R/W I [31:16] non-cacheable0CoOoAE1/41/2aOO* 0x00000000 non-cacheable1CoOoAE1/41/2aOO*1 0x00000000 AeEo non-cacheable0A1/2aEoOO*OoIon-cacheable cI4Kbyte SA0 [15:0] OoESE0 1/4AEEaEcIA. AxicI SE0 = (End address + 1)/4K non-cacheable0AE1/4OO*OoIon-cacheable 4KbyteOoESA0 SE1 [31:16] 1/4AEEaEcIA. Axi SA0 = Start address/4K non-cacheable1A1/2aEoOO*OoIon-cacheable cI4Kbyte SA1 [15:0] OoESE1 1/4AEEaEcIA. AxicI SE1 = (End address + 1)/4K non-cacheable1AE1/4OO*OoIon-cacheable Axi [0] IONIiOUEOACache, OEiIONIi OEiIONIi. uE*CAoOOE, IAE1/4oOI0. aEeOo1/4ayOUAEU 4KbyteOoESA0 3 IAuAE FIX IIxUOAE1/4OOAEAae/ xUIOAE1/4OOAEAae/ AeEo OAIE1/4AE1/2 1/4AEEaEcIA. SA1 = Start address/4K SBUSCON 0x01C40000 R/W I [31] oE1/4O 0x80001B1B 0: round-robin priorities 1: fixed priorities S_LCD_DMA S_ZDMA S_BDMA S_nBREQ LCD_DMA ZDMA BDMA nBREQ [15:14] [13:12] [11:10] [9:8] [7:6] [5:4] [3:2] [1:0] OE3/4 LCD_DMA OE3/4ZDMA OE3/4BDMA OE3/4 nBREQ E*LCD_DMA E*ZDMA E*BDMA E*nBREQ xUIOAE1/4 xUIOAE1/4 xUIOAE1/4 AOAIE1/4OA(c) AOAIE1/4OA(c) xUIOAE1/4 AxUIOAE1/4OA(c) AxUIOAE1/4OA(c) 00: 1st 01: 2nd 10: 3rd 11: 4th 00: 1st 01: 2nd 10: 3rd 11: 4th 00: 1st 01: 2nd 10: 3rd 11: 4th 00: 1st 01: 2nd 10: 3rd 11: 4th 00: 1st 01: 2nd 10: 3rd 11: 4th 00: 1st 01: 2nd 10: 3rd 11: 4th 00: 1st 01: 2nd 10: 3rd 11: 4th 00: 1st 01: 2nd 10: 3rd 11: 4th 7 DMA S3C44B0XO4 A*DMA OOAE/aA1/2A*IZDMA General DMA (c)A1/2 DMA ZDMAI IOaeAE/ xOAIaEe(c)OeaeAE/(R)1/4aEy3/4Y on-the-flyAE1/2 IOoEOO1/4oUUaaeAE/NO*Ae(R)aDMA S3C44B0X OOo4 EaOoEaeAE/O(R)1/4Ay3/4YxiAOZDMA -Oe Ceo/ O|-Oe CeoOUAAE1/2DMA Ux/IeECAUNIEAoAEaEuOOEOOInXDREQ EaEOOCoxO1/2Ueo(c) Ux/AEU1/4aAAOUE* Ce OEAOAaIaDMA xOAFIFOaAO4 xOI*DMA EaAIa(c)AEUE EaoBDMA on-the-flyAOUAEUAAE*iE1/2O DMA aEIZ OUOa Ux/AOUAEU O IOxEy3/4YO(R)1/4aAE/A1/2ae BDMA SSB(Samsung System Bus)xUIEAiIa1/2A*AEIBDMA SPB(Samsung Peripheral Bus)OAEICAOoE oOUIa a1/2(R)1/4aA BDMA1/4EOOOOAiAEoAUIaeCeoy1/2AA ZDMAOAE/1/2ae AE/ae1/2AOUA OOAE/AUOUA1/2SPBEIAIO ZDMAxCOEOIAoi OeAEOIADMA Ey OOUZDMA I*DMA OOUZDMA IOEOA1/2 OoAAO|ODMA iOoEOUoDMA CoOyAEIDMA 1/2AE Bridge DMA (c)ECSSBI 2 IaDMA REQ/ACK 1/2AEOaIxADMA DMAAIOUAEU/OOAeaEOA1/2(R)1/4axIOEEoEu xUIOOAE/ Whole Service Mode OIDMA OUAAE1/2 EaAEU1/4nXDACK EI*AOIxUIOOAEEOaaEu/OuaEO1/4A Demand Mode ODMA O OUAAE1/2 OoEO|AO*AEaOUAEUyaeAxio1/4 OEyODMA Unit EaA1/2 BlockEaA1/2 On-the-fly EaA1/2 DMA1/4AaeAE/ 1 ZDMAOOAE1/4Aae/ 0x01E80000 0x01E80020 AeEo [7:6] [5:4] ZDCON0 ZDCON1 IAuAE INT STE BIT EaA1/2IeOn the fly 1 4 1 OAOOCoe ADMA AoCo1/2uEe OOODMA EaOA1/2oDMA O|OUAEUuEA1/2oA nXDACK(c)OE3/4 aE CeoAEI*OOUAIaoy3/4Y ADMAEaIey MA O1/2ae OUD DMAIOOAEEOAxUCOO1/4 Oo1/2Ea3/4I eEaA1/2(c) oIA, oxOI*A, 16xO1/2UAEy oIAo 1 oIAIE1/2o Eo 1 Eo4 oI oxOI*OoEEaAy3/4YO|C R/W R/W Ao 00 DMAIAAxIOA(c) OUDMA AEa1/4AEyO(R)CSTE ZDMA 0 OOAE1/4Aae/ oE1/4O 0x00 ZDMA 1 OOAE1/4Aae/ oE1/4O 0x00 oOUx1/4AI 00 = Ready 10 = Terminal Count QDS CMD 00: AOuAi. 01: OES/W 10: IODMA 11: EIuDMA 2 ZDISRC0 ZDIDES0 ZDICNT0 3 ZDCSRC0 ZDCDES0 ZDCCNT0 4 [3:2] [1:0] OU 01,10,11 AEoDMA Ux/. Ux/ AeOO*I1/4AEEy ae / 0x01E80004 0x01E80008 0x01E8000C AeOO*I1/4AEEy ae / 0x01E80010 0x01E80014 0x01E80018 AeOO*I1/4AEEy ae / Ux/ S/W 01 = Not TC yet 11 = N/A oAa/ 00 = Enable Ei1/4AuAi o, CMD IxOCay nXDREQOEi AEo|AUOAOUwhole mode. OEiIa DMA Ceo (nXDREQ) other = Disable nXDREQEOEi ZDMA0 oE1/4O/ R/W R/W ZDMA 0oE1/4OOO*AaeAE/ ZDMA 0oE1/4AeOO*aeAE/ oE1/4O 0x00000000 oE1/4O 0x00000000 oE1/4O 0x00000000 R/W ZDMA 0oE1/4AEyAae/ R R ZDMA 0COOO*1/4AaeAE/ oE1/4O 0x00000000 ZDMA 0 C1/4AEEyAae/ ZDMA0 CO/ R ZDMA 0CAeOO*1/4aeAE/ oE1/4O 0x00000000 oE1/4O 0x00000000 ZDMA1 oE1/4O/ ZDISRC1 ZDIDES1 0x01E80024 0x01E80028 R/W R/W ZDMA 1oE1/4OOO*AaeAE/ ZDMA 1oE1/4AeOO*aeAE/ oE1/4O 0x00000000 oE1/4O 0x00000000 ZDICNT1 5 ZDCSRC1 ZDCDES1 ZDCCNT1 ZDMAnAoE1/4COOO*aeAE/IOa IAuAE DST 0x01E8002C AeOOO*I1/4AEEy A ae / 0x01E80030 0x01E80034 0x01E80038 BIT [31:30] R/W ZDMA 1oE1/4AEyAae/ R R ZDMA 1COOO*1/4AaeAE/ oE1/4O 0x00000000 ZDMA 1 C1/4AEEyAae/ AeEo EaAy3/4YAaIOUe1/2DSTOeEC10 oE1/4O 0x00000000 ZDMA1 C/ R ZDMA 1CAeOO*1/4aeAE/ oE1/4O 0x00000000 oE1/4O 0x00000000 00 = Byte, 01 = Half word 10 = Word, 11 = Not used DAL [29:28] 1/4OOOO*a1/2Io 00 = N/A, 01 = Increment 10 = Decrement, 11 = Fixed ISADDR/CSADDR ZDMAnAoE1/4CeOO*aeAE/IOa IAuAE OPT bit 31: OE3/4OU1/2A nXDREQ bit 30: EcuDSTECexOoI DMA 1: DMAxoxOoe1/2 EaC: B0,B1,B2,B3,B4,B5,B6,B7... xO1/2o: B3,B2,B1,B0,B7,B6,B5,B4,... exO1/2o: B1,B0,B3,B2,B5,B4,B7,B6,... 0: Oy DAS [29:28] 10 = Decrement 11 = Fixed IDADDR/CDADDR ZAMA1/4AEEy1/4Aae/IOa IAuAE QSC 00 = nXDREQ[0] 10 = N/A QTY 00 = Handshake 10 = Whole Service TMD [27:26] 00 = Not used OTF 00 = N/A INTS 00 = eNAE1/2 [23:22] 01 = N/A OIAE1/2EeA [25:24] BIT [31:30] NOnDMA AeEo CeoO 01 = nXDREQ[1] 11 = N/A [29:28] DREQ -OeAaI 01 = Single step 11 = Demand EaA1/2 01 = Unit transfer mode On the fly mode O 01 = N/A [27:0] ZDMAnAoE1/4/ CAeOO* OO*1/2Io 00 = N/A 01 = Increment BIT [31:30] EcIENu AE1/2CeaAIAEx/O AeEo DMAAUNIiIAE1/4oO OPT = 10 [27:0] ZDMAnAoE1/4/ COOO* 10 = Block(4-word) transfer mode 11 = On the fly 10 = Read time on the fly 11 = Write time on the fly 10 =IAUEAoa1/4uEOI 11 =OI1/4AEEyuE AR [21] 0 = Disable 1 = Enable. EN [20] DMA H/WOEi/ OEi 0 = Disable DMA 1 = Enable DMA. Ecu S/W OUOI1/4AEEyEN x :OIEEeOAZDICNTD OUDMA 1/4AEEy1/20 ExO1/4OOI AuAiEIu, DMA IOCay A Ux/O1/2EIuIEN ENIIAEaEuI OAOeOUEeOAEaEuIoAEN ICay I1/2OeEcIA 1. Set ZDICNT register with disabled En bit. 2. Set EN bit enable. ICNT/CCNT [19:0] ZDMAnAoE1/4/ EcuEaIxO1/2UICNT EcuEaIexOICNT EcuEaIxOICNT CEa1/4AEyO. AI1/4o1 AI1/4o2 AI1/4o4 BDMA 0 OOAE1/4Aae/ oE1/4O 0x00 BDMA 1 OOAE1/4Aae/ oE1/4O 0x00 OeOyE*EeOA 6 BDMAOOAE1/4Aae/ 0x01F80000 0x01F80020 AeEo [7:6] [5:4] Ao 00 DMAIAAxIOA(c) OUDMA AEa1/4AEyO(R)CSTE 00 = Ready 10 = Terminal Count QDS CMD [3:2] [1:0] OU 01,10,11 oAa/ 00 = Enable Ei1/4AuAi o, CMD IxOCay 01 = Not TC yet 11 = N/A OEiIa DMA Ceo (nXDREQ) other = Disable oOUx1/4AI R/W R/W BDCON0 BDCON1 IAuAE INT STE BIT 00: AOuAi. 01: Ao 10: Ao 11: EIuDMA 7 BDISRC0 BDIDES0 BDICNT0 8 BDCSRC0 BDCDES0 BDCCNT0 9 Ux/ AeOO*I1/4AEEy ae / R/W R/W BDMA 0oE1/4OOO*AaeAE/ BDMA 0oE1/4AeOO*aeAE/ oE1/4O 0x00000000 oE1/4O 0x00000000 oE1/4O 0x00000000 0x01F80004 0x01F80008 0x01F8000C AeOO*I1/4AEEy ae / R R BDMA 0COOO*1/4AaeAE/ oE1/4O 0x00000000 BDMA 0 C1/4AEEyAae/ oE1/4O 0x00000000 R BDMA 0CAeOO*1/4aeAE/ oE1/4O 0x00000000 0x01F80010 0x01F80014 0x01F80018 AeOO*I1/4AEEy ae / R/W BDMA 1oE1/4OOO*AaeAE/ oE1/4O 0x00000000 BDMA0 oE1/4O/ R/W BDMA 0oE1/4AEyAae/ BDMA0 CO/ BDMA1 oE1/4O/ BDISRC1 0x01F80024 BDIDES1 BDICNT1 BDCSRC1 BDCDES1 BDCCNT1 BDMAnAoE1/4COOO*aeAE/IOa IAuAE DST 0x01F80028 0x01F8002C AeOOO*I1/4AEEy A ae / 0x01F80030 0x01F80034 0x01F80038 BIT [31:30] R/W BDMA 1oE1/4AeOO*aeAE/ oE1/4O 0x00000000 oE1/4O 0x00000000 R/W BDMA 1oE1/4AEyAae/ R R BDMA 1COOO*1/4AaeAE/ oE1/4O 0x00000000 BDMA 1 C1/4AEEyAae/ AeEo EaAy3/4YAaI 10 BDMA1 C/ R BDMA 1CAeOO*1/4aeAE/ oE1/4O 0x00000000 oE1/4O 0x00000000 00 = Byte, 01 = Half word 10 = Word, 11 = Not used DAL [29:28] 1/4OOOO*a1/2Io 00 = N/A, 01 = Increment 10 = Decrement, 11 = Fixed ISADDR/CSADDR BDMAnAoE1/4CeOO*aeAE/IOa IAuAE TDM 00 = Ao 01 = M2IO (OIaaeAE/1/2AUEe) 10 = IO2M (OAUIaEe1/2aeAE/) 11= IO2IO (OAUIaEe1/2) x1/4EOABAMA DAS 00 = N/A IDADDR/CDADDR BAMA1/4AEEy1/4Aae/IOa IAuAE QSC 00 = N/A 10 = UART0 Reserved Reserved Reserved INTS 00 = eNAE1/2 10 =IAUEAoa1/4uEOI 11 =OI1/4AEEyuE AR [21] 0 = Disable 1 = Enable. OUDMA 1/4AEEy1/20 ExO1/4OOI 00 = Handshake [27:26] [25:24] [23:22] 01 = N/A OIAE1/2EeA EaA1/2 00 = N/A 01 = Unit transfer mode BIT [31:30] 01 = IIS 11 = SIO [29:28] NOnDMA AeEo CeoO IAAaOOeaAO [29:28] OO*1/2Io 01 = Increment [27:0] BDMAnAoE1/4/ CAeOO* BIT [31:30] Ea*1/2IoA AeEo [27:0] BDMAnAoE1/4/ COOO* 10 = Decrement 11 = Fixed EN [20] DMA H/WOEi/ OEi 0 = Disable DMA 1 = Enable DMA. Ecu S/W OUOI1/4AEEyEN x :OIEEeOABDICNTD AuAiEIu, DMA IOCay A Ux/O1/2EIuIEN ENIIAEaEuI OAOeOUEeOAEaEuIoAEN ICay I1/2OeEcIA 1. Set BDICNT register with disabled En bit. 2. Set EN bit enable. ICNT/CCNT [19:0] BDMAnAoE1/4/ EcuEaIxO1/2UICNT EcuEaIexOICNT EcuEaIxOICNT CEa1/4AEyO. AI1/4o1 AI1/4o2 AI1/4o4 8 I/O PORTS S3C44B0XO71oI|AUI/O EUE EUD EUC EUA EUB OUO/IoE1/4COeOaAoI/O Port A Function 1 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB9 PB8 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 output output output output output output output output output output output output output output output output output output output output Function 2 ADDR24 ADDR23 ADDR22 ADDR21 ADDR20 ADDR19 ADDR18 ADDR17 ADDR16 ADDR0 nGCS5 nGCS4 nGCS3 nGCS2 nGCS1 nWBE3:nBE3:DQM3 nWBE2:nBE2:DQM2 nSRAS:nCAS3 nSCAS:nCAS2 SCLK SCKE Function 3 Function 4 IF9 IG8 16II/O 10II/O 11II/O U(c) U1/2AA|OUIOEaOAx/II/O 1/2AEOA U(c) II/O II/O U(c) U(c) U(c) UOy1/2A*OE7 oEU PB10 output PC15 Input/output PC14 Input/output PC13 Input/output PC12 Input/output PC11 Input/output PC10 Input/output PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PE8 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 PF8 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 PG7 PG6 Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output ENDIAN Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output input/output input/output input/output input/output input/output input/output input/output input/output input/output input/output input/output DATA31 DATA30 DATA29 DATA28 DATA27 DATA26 DATA25 DATA24 DATA23 DATA22 DATA21 DATA20 DATA19 DATA18 DATA17 DATA16 VFRAME VM VLINE VCLK VD3 VD2 VD1 VD0 CODECLK TOUT4 TOUT3 TOUT2 TOUT1 TOUT0 RxD0 TxD0 Fpllo nCTS1 RxD1 TxD1 nRTS1 nXBREQ nXBACK nWAIT - - IICSDA - - IICSCL IISLRCK IISDO nCTS0 nRTS0 RxD1 TxD1 nCTS1 nRTS1 nXDREQ1 nXDACK1 VD4 VD5 VD6 VD7 IISCLK IISDI IISDO IISLRCK input/output VD7 VD6 TCLK TCLK Fout SIOCK SIORxD SIORDY SIOTxD nXDREQ0 - nXDACK0 - IISCLK IISDI IISDO IISLRCK EINT7 EINT6 PG5 PG4 PG3 PG2 PG1 PG0 I/OEUOOAE1/4Aae/ input/output input/output input/output input/output input/output input/output IISDI IISCLK nRTS0 nCTS0 VD5 VD4 EINT5 EINT4 EINT3 EINT2 EINT1 EINT0 1 PORT A OOAE1/4Aae/ PCONA PDATA IAuAE PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 Ey3/4Y1/4AaeAE/IAeo PA[9:0] 2 PORT B OOAE1/4Aae/ PCONB PDATB IAuAE PB10 PB9 PB8 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 Ey3/4Y1/4AaeAE/IAeo PB[10:0] 3 PORT C OOAE1/4Aae/ PCONC 0x01D20010 R/W port CAAaOA oE1/4O 0xaaaaaaaa [10:0] EUAaOAx/I|AU1/2EEcuACOo* EUAaOAIEoOO|1/2AxIIIa 0x01D20008 0x01D2000C BIT [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] R/W R/W AeEo 0 = Output 1 = nGCS5 0 = Output 1 = nGCS4 0 = Output 1 = nGCS3 0 = Output 1 = nGCS2 0 = Output 1 = nGCS1 0 = Output 1 = nWBE3/nBE3/DQM3 0 = Output 1 = nWBE2/nBE2/DQM2 0 = Output 1 = nSRAS/nCAS3 0 = Output 1 = nSCAS/nCAS2 0 = Output 1 = SCLK 0 = Output 1 = SCKE port BAAaOA port BAEy3/4Y1/4aeAE/ oE1/4O Undef. oE1/4O 0x7ff [9:0] EUAaOAx/I|AU1/2EEcuACOo* EUAaOAIEoOO|1/2AxIIIa 0x01D20000 0x01D20004 BIT [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] R/W R/W AeEo 0 = Output 1 = ADDR24 0 = Output 1 = ADDR23 0 = Output 1 = ADDR22 0 = Output 1 = ADDR21 0 = Output 1 = ADDR20 0 = Output 1 = ADDR19 0 = Output 1 = ADDR18 0 = Output 1 = ADDR17 0 = Output 1 = ADDR16 0 = Output 1 = ADDR0 port AAAaOA port AAEy3/4Y1/4aeAE/ oE1/4O Undef. oE1/4O 0x3ff PDATC PUPC IAuAE PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 [1:0] Ey3/4Y1/4AaeAE/IAeo PC[15:0] 0x01D20014 0x01D20018 BIT [31:30] [29:28] [27:26] [25:24] [23:22] [21:20] [19:18] [17:16] [15:14] [13:12] [11:10] [9:8] [7:6] [5:4] [3:2] R/W R/W AeEo port CAEy3/4Y1/4aeAE/ port CAEIA-cxeAaOA1/4aeAE/ oE1/4O0x0 00 = Input 01 = Output 10 = DATA31 11 = nCTS0 00 = Input 01 = Output 10 = DATA30 11 = nRTS0 00 = Input 01 = Output 10 = DATA29 11 = RxD1 00 = Input 01 = Output 10 = DATA28 11 = TxD1 00 = Input 01 = Output 10 = DATA27 11 = nCTS1 00 = Input 01 = Output 10 = DATA26 11 = nRTS1 00 = Input 01 = Output 10 = DATA25 11 = nXDREQ1 00 = Input 01 = Output 10 = DATA24 11 = nXDACK1 00 = Input 01 = Output 10 = DATA23 11 = VD4 00 = Input 01 = Output 10 = DATA22 11 = VD5 00 = Input 01 = Output 10 = DATA21 11 = VD6 00 = Input 01 = Output 10 = DATA20 11 = VD7 00 = Input 01 = Output 10 = DATA19 11 = IISCLK 00 = Input 01 = Output 10 = DATA18 11 = IISDI 00 = Input 01 = Output 10 = DATA17 11 = IISDO 00 = Input 01 = Output 10= DATA16 11 = IISLRCK oE1/4O Undef. [15:0] EUAaOAx/I|AU1/2EEcuACOo* EUAaOAIEEeACOO|1/2xI EUAaOAIEoOO|1/2AxIIIa EIA-cxeAaOA1/4AaeAE/IEo PC[15:0] 4 PORT D OOAE1/4Aae/ PCOND 0x01D2001C R/W port DAAaOA oE1/4O 0x0000 [15:0] 0: OEiEIA-cxeA1/2O|A 1: OEi. PDATD PUPD IAuAE PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 [1:0] Ey3/4Y1/4AaeAE/IAeo PD[15:0] 0x01D20020 0x01D20024 BIT [15:14] [13:12] [11:10] [9:8] [7:6] [5:4] [3:2] R/W R/W AeEo port DAEy3/4Y1/4aeAE/ port DAEIA-cxeAaOA1/4aeAE/ oE1/4O0x0 00 = Input 01 = Output 10 = VFRAME 11 = Reserved 00 = Input 01 = Output 10 = VM 11 = Reserved 00 = Input 01 = Output 10 = VLINE 11 = Reserved 00 = Input 01 = Output 10 = VCLK 11 = Reserved 00 = Input 01 = Output 10 = VD3 11 = Reserved 00 = Input 01 = Output 10 = VD2 11 = Reserved 00 = Input 01 = Output 10 = VD1 11 = Reserved 00 = Input 01 = Output 10= VD0 11 = Reserved oE1/4O Undef. [15:0] EUAaOAx/I|AU1/2EEcuACOo* EUAaOAIEEeACOO|1/2xI EUAaOAIEoOO|1/2AxIIIa EIA-cxeAaOA1/4AaeAE/IEo PD[15:0] 5 PORT E OOAE1/4Aae/ PCONE PDATE PUPE IAuAE PE8 PE7 PE6 PE5 PE4 PE3 PE2 0x01D20028 0x01D2002C 0x01D20030 BIT [17:16] [15:14] [13:12] [11:10] [9:8] [7:6] [5:4] R/W R/W R/W AeEo 00 = Reserved(ENDIAN) 01 = Output 10 = CODECLK 11 = Reserved 00 = Input 01 = Output 10 = TOUT4 11 = VD7 00 = Input 01 = Output 10 = TOUT3 11 = VD6 00 = Input 01 = Output 10 = TOUT2 11 = TCLK in 00 = Input 01 = Output 10 = TOUT1 11 = TCLK in 00 = Input 01 = Output 10 = TOUT0 11 = Reserved 00 = Input 01 = Output port EAAaOA port EAEy3/4Y1/4aeAE/ port EAEIA-cxeAaOA1/4aeAE/ oE1/4O0x00 oE1/4O 0x00 oE1/4O Undef. [15:0] 0: OEiEIA-cxeA1/2O|A 1: OEi. 10 = RxD0 11 = Reserved PE1 PE0 Ey3/4Y1/4AaeAE/IAeo PE[8:0] EIA-cxeAaOA1/4AaeAE/IEo PE[7:0] [7:0] 0: OEiEIA-cxeA1/2O|A 1: OEi. PE8AOEaIAIA-cxe 6 PORT F OOAE1/4Aae/ PCONF PDATF PUPF IAuAE PF8 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 Ey3/4Y1/4AaeAE/IAeo PF[8:0] [8:0] EUAaOAIEEeACOO|1/2xI EUAaOAIEoOO|1/2AxIIIa AOoE*1/2ECO AOAAIEcu 1/2AEx/I|AUEUaOA EIA-cxeAaOA1/4AaeAE/IEo PF[8:0] 7 PORT G OOAE1/4Aae/ PCONG 0x01D20040 R/W port GAAaOA oE1/4O 0x0 [8:0] 0: OEiEIA-cxeA1/2O|A 1: OEi. 0x01D20034 0x01D20038 0x01D2003C BIT [21:19] [18:16] [15:13] [12:10] [9:8] [7:6] [5:4] [3:2] [1:0] R/W R/W R/W AeEo 000 = Input 001 = Output 010 = nCTS1 011 = SIOCLK 100 = IISCLK Others = Reserved 000 = Input 001 = Output 010 = RxD1 011 = SIORxD 100 = IISDI Others = Reserved 000 = Input 001 = Output 010 = TxD1 011 = SIORDY 100 = IISDO Others = Reserved 000 = Input 001 = Output 010 = nRTS1 011 = SIOTxD 100 = IISLRCK Others = Reserved 00 = Input 01 = Output 10 = nXBREQ 11 = nXDREQ0 00 = Input 01 = Output 10 = nXBACK 11 = nXDACK0 00 = Input 01 = Output 10 = nWAIT 11 = Reserved 00 = Input 01 = Output 10 = IICSDA 11 = Reserved 00 = Input 01 = Output 10= IICSCL 11 =Reserved port FAAaOA port FAEy3/4Y1/4aeAE/ port FAEIA-cxeAaOA1/4aeAE/ oE1/4O0x000 oE1/4O 0x0000 oE1/4O Undef. [8:0] EUAaOAIEoOO|1/2AxIIIa AOoE*1/2ECO AOAAIEcu 1/2AEx/I|AUEUaOA [3:2] [1:0] 00 = Input 01 = Output 10 = TxD0 11 = Reserved 00 = Input 01 = Output 10= Fpllo out 11 = Fout out PDATG PUPG IAuAE PG7 PG6 PG5 PG4 PG3 PG2 PG1 PG0 Ey3/4Y1/4AaeAE/IAeo PG[7:0] 0x01D20044 0x01D20048 BIT [15:14] [13:12] [11:10] [9:8] [7:6] [5:4] [3:2] [1:0] R/W R/W AeEo port GAEy3/4Y1/4aeAE/ port GAEIA-cxeAaOA1/4aeAE/ oE1/4O0x0 00 = Input 01 = Output 10 =IISLRCK 11 = EINT7 00 = Input 01 = Output 10 = IISDO 11 = EINT6 00 = Input 01 = Output 10 = IISDI 11 = EINT5 00 = Input 01 = Output 10 = IISCLK 11 = EINT4 00 = Input 01 = Output 10 = nRTS0 11 = EINT3 00 = Input 01 = Output 10 = nCTS0 11 = EINT2 00 = Input 01 = Output 10 = VD5 11 = EINT1 00 = Input 01 = Output 10 = VD4 11 = EINT0 oE1/4O Undef. [7:0] EUAaOAIEEeACOO|1/2xI EUAaOAIEoOO|1/2AxIIIa AOoE*1/2ECO AOAAIEcu 1/2AEx/I|AUEUaOA EIA-cxeAaOA1/4AaeAE/IEo PG[7:0] 8 EIA-cxeOOAE1/4Aae/ OOAED[150] SPUCR IAuAE HZ@STOP SPUCR1 SPUCR0 8 IAuAE EINT7 IaOIOAE1/4Aae/ 0x01D20050 BIT [30:28] R/W AeEo 000 = IcAE1/2* 001 = 01x = IA1/2NO* 10x = EIyNO* 11x =ENO* EINT6 [26:24]. 000 = IcAE1/2* 001 = 01x = IA1/2NO* 10x = EIyNO* 11x =ENO* cAE1/2OI cAE1/2OI IaOIOAE1/4Aae/ oE1/4O 0x000000 0x01D2004C BIT [2] [1] [0 0 =OUIOAE1/2aeAE/OAIECxI 1 = OOAEAxeI 0 = DATA[15:8] EIA-cxeOEi 1 = DATA[15:8] EIA-cxeOEi 0 = DATA[7:0] EIA-cxeOEi 1 = DATA[7:0] EIA-cxeOEi EXTINT R/W AeEo [7:0] 0: OEiEIA-cxeA1/2O|A 1: OEi. 1/2AAEIA-cxe EIA-cxeOOAE1/4Aae/ oE1/4O 0x4 EINT5 [22:20] 000 = IcAE1/2* 001 = 01x = IA1/2NO* 10x = EIyNO* 11x =ENO* cAE1/2OI EINT4 [18:16] 000 = IcAE1/2* 001 = 01x = IA1/2NO* 10x = EIyNO* 11x =ENO* cAE1/2OI EINT3 [14:12] 000 = IcAE1/2* 001 = 01x = IA1/2NO* 10x = EIyNO* 11x =ENO* cAE1/2OI EINT2 [10:8] 000 = IcAE1/2* 001 = 01x = IA1/2NO* 10x = EIyNO* 11x =ENO* cAE1/2OI EINT1 [6:4] 000 = IcAE1/2* 001 = 01x = IA1/2NO* 10x = EIyNO* 11x =ENO* cAE1/2OI EINT0 [2:0] 000 = IcAE1/2* 001 = 01x = IA1/2NO* 10x = EIyNO* 11x =ENO* cAE1/2OI 9 IaOIOAE1/4Aae/ IaOICeo4 5 6 7 IyoA1/4-OAOoOICeo EXTINTPND 0x01D20054 IAuAE BIT EXTINTPND3 [3] Ecu EINT7 EXTINTPND2 [2] Ecu EINT6 EXTINTPND1 [1] Ecu EINT5 EXTINTPND0 [0] Ecu EINT4 OI*InIOeOUCayIaOAEo1/4EXTINTPNDoCayOIOAEIo1/4INTPND(c) EXTINTPNDIyEe1 ACay AeEo R/W IaOIOAE1/4Aae/ oE1/4O 0x00 OEeOAI1 1/4i, EXINTPND3EeOAI1, INTPND[21] 1/4i, EXINTPND2EeOAI1, INTPND[21]OEeOA1 1/4i, EXINTPND1EeOAI1, INTPND[21]OEeOA1 1/4i, EXINTPND0EeOAI1, INTPND[21]OEeOAI1 9 EAE/0 8IAE/0 E eO PWM TIMER AE1/2Ax/AE0 ECOoAUAE/AOa1/2A0 AE/2 E eIO 3Oo8 IiA IOoEaEeOOTCLK/EXTCLK. 4 /AEEeOI EAE/4 1 2 3OAE/(1/2, 1/4, 1/8, 1/16, 1/32). EOOy*oO OOoDEAD ZONE 1 uEAE/ 5OoIiO 5OoO 2 3 4 1IiOo8 S3C44B0XOAuo16IEAE/AoEOOOIA1/2oDMA OPWM |AUEAE/5 EOOy*AE/(1/2, 1/4, 1/8, 1/16) AoEAE/OOy*1/2OaEeoAIIa|Oe AoEAE/OO1/4yaAaeOoOiIEuIoA 1/4AE1/20 a1/4AaeAE/oEOOOO1/2EIeoAya IEAE/OOA1/4-AaTOUT OEUEaIOO/TCMPn 8IOeAE/I4 IEOOy*AE/EOOIAAo 1/2IoEAE/OOEA CoIeuEO AE/IoA1/4EyAOO1/2OoOA E AEaocAE1/2 ITCNTBn EOOEaeE1/4OOUIAoOUAEx/A (prescaler = 255) (TCNTBn = 65535) 0.50 sec 4-bit divider settings (prescaler = 1) 1/2 ( MCLK = 66 MHz ) 0.030 us (33.0 MHz ) 7.75 us (58.6 KHz ) 1/4 ( MCLK = 66 MHz ) 0.060 us (16.5 MHz ) 15.5 us (58.6 KHz ) 1/8 ( MCLK = 66 MHz ) 0.121 us (8.25 MHz ) 31.0 us (29.3 KHz ) 1/16 ( MCLK = 66 MHz) 0.242 us (4.13 MHz) 62.1 us (14.6 KHz ) 1/32 ( MCLK = 66 MHz) 0.485 us (2.06 MHz) 125 us (7.32 KHz ) IAUEIAE/C*nOETOUT DEAD ZONE uEAE/ DEAD ZONE uEAE/ETOUT0 OOoA1/4aI DMA CeoAE1/2 PWMEAE/AUOUae1/4auEOoDMA AIIyEeOATCFG11/4AaeAE/6 DMA mode DMA request AaOA DMA mode DMA request 0000 0001 0010 0011 0100 0101 0110 0111 EAE/OO1/4Aae 1 IAuAE Dead zone length Prescaler 2 Prescaler 1 Prescaler 0 2 IAuAE DMA mode EAE/AaOA1/4Aae1 0x01D50004 BIT [27:24] R/W MUXIDMA AE1/2NOn1/4aeAE/ oE1/4O AeEo NOnDMA 0010 = Timer1 CeoIA 0011 = Timer2 0x00000000 TCFG1 EAE/AaOA1/4Aae0 0x01D50000 BIT [31:24] [23:16] [15:8] [7:0] 1/4aIOeEAE/0 Oa8 Oa8 Oa8 IE*EAE/4 IE*EAE/2 IE*EAE/0 R/W Eyo 8 AeEo Oa 8 IE*dead zone AOoE1/4aIIaE. 5 3 1 AOeAE/O AOeAE/O AOeAE/O AE. dead zone IOeAE/AAaOA oE1/4O TCFG0 No select Timer0 Timer1 Timer2 Timer3 Timer4 Timer5 No select CeoEAE/OUO1/2ACK oEAE/O(R)OAUuEDMA AO(R)CODMA CeoOUuEOI InTOUT0 TOUT0A*xA(c)EaoUIooCO(R)1/4 *xAE/A on/off IaTOUT A1/4-a 1.02 sec 2.03 sec 4.07 sec 8.13 sec CeoA 0x00000000 AEOoE 0000 = No select (all interrupt) 0001 = Timer0 0100 = Timer3 0101 = Timer4 0110 = Timer5 0111 = Reserved MUX 5 [23:20] NOnEAE/5 AMUX EaEe . 0001 = 1/4 AMUX EaEe. 0001 = 1/4 0010 = 1/8 0010 = 1/8 01xx = EXTCLK 0000 = 1/2 0011 = 1/16 MUX 4 [19:16] NOnEAE/4 0000 = 1/2 0011 = 1/16 MUX 3 [15:12] NOnEAE/3 0000 = 1/2 MUX 2 [11:8] NOnEAE/2 0000 = 1/2 0011 = 1/16 MUX 1 [7:4] NOnEAE/1 0000 = 1/2 0011 = 1/16 MUX 0 [3:0] NOnEAE/0 0000 = 1/2 0011 = 1/16 3 IAuAE Timer 5 auto reload on/off Timer 5 manual update Timer 5 start/stop 0 = Stop Timer 4 auto reload on/off Timer 4 outputinverter on/off Timer 4 manual update Timer 4 start/stop 0 = Stop Timer 3 auto reload on/off Timer 3 outputinverter on/off Timer 3 manual update Timer 3 start/stop 0 = Stop Timer 2 auto reload on/off Timer 2 outputinverter on/off Timer 2 manual update EAE/OO1/4Aae 0x01D50008 R/W BIT [26] OaIE*EAE/5 [25] [24] [23] OaIE*EAE/4 [22] OaIE*EAE/4 [21] [20] [19] OaIE*EAE/3 [18] OaIE*EAE/3 [17] [16] [15] OaIE*EAE/2 [14] OaIE*EAE/2 [13] OaIE*EAE/2 OaIE*EAE/3 OaIE*EAE/3 OaIE*EAE/4 OaIE*EAE/5 OaIE*EAE/5 OaIE*EAE/5 0 = One-shot 0 = No operation EAE/OO1/4Aae TCON 01xx = TCLK AMUX EaEe. 0001 = 1/4 AMUX EaEe. 0001 = 1/4 01xx = 1/32 AMUX EaEe. 0001 = 1/4 01xx = 1/32 AMUX EaEe. 0001 = 1/4 01xx = 1/32 oE1/4O AeEo AxO1/4OO/ AEOuA 1 = Update TCNTB5 AAEo/ AxO1/4OO/ AEao*xAE// 1 = Inverter on for TOUT4 AEOuA 1 = Update TCNTB4TCMPB4 AAEo/ AxO1/4OO/ AEao*xAE// 1 = Inverter on for TOUT3 AEOuA 1 = Update TCNTB3TCMPB3 AAEo/ AxO1/4OO/ AEao*xAE// 1 = Inverter on for TOUT2 AEOuA 1 = Update TCNTB2TCMPB2 IO. O O IO. O O IO. O O O 1 = Interval mode (auto reload) 0x00000000 0010 = 1/8 0010 = 1/8 0010 = 1/8 0010 = 1/8 0011 = 1/16 01xx = 1/32 1 = Start for Timer 5 1 = Interval mode (auto reload) 0 = One-shot 0 = Inverter off 0 = No operation 1 = Start for Timer 4 1 = Interval mode (auto reload) 0 = One-shot 0 = Inverter off 0 = No operation 1 = Start for Timer 3 1 = Interval mode (auto reload) 0 = One-shot 0 = Inverter off 0 = No operation Timer 2 start/stop 0 = Stop Timer 1 auto reload on/off Timer 1 outputinverter on/off Timer 1 manual update Timer 1 start/stop 0 = Stop Dead zone enable Timer 0 auto reload on/off Timer 0 outputinverter on/off Timer 0 manual update Timer 0 start/stop 0 = Stop 4 EAE/0 1/4AEEy/ E1/2Ia1/4AaeAE/ 0x01D5000C 0x01D50010 1/4AEEyUiAae/ 0x01D50014 1/4AEEy/ E1/2Ia1/4AaeAE/ 0x01D50018 0x01D5001C 1/4AEEyUiAae/ 0x01D50020 1/4AEEy/ E1/2Ia1/4AaeAE/ 0x01D50024 0x01D50028 1/4AEEyUiAae/ 0x01D5002C 1/4AEEy/ E1/2Ia1/4AaeAE/ 0x01D50030 0x01D50034 1/4AEEyUiAae/ 0x01D50038 1/4AEEy/ E1/2Ia1/4AaeAE/ 0x01D5003C 0x01D50040 1/4AEEyUiAae/ R R R R TCNTB0 TCMPB0 5 EAE/0 TCNTO0 6EAE/1 TCNTB1 TCMPB1 7 EAE/1 TCNTO1 8 EAE/2 TCNTB2 TCMPB2 9 EAE/2 TCNTO2 10 EAE/3 TCNTB3 TCMPB3 11 EAE/3 TCNTO3 12EAE/4 TCNTB4 TCMPB4 13 EAE/4 [12] [11] OaIE*EAE/1 [10] OaIE*EAE/1 [9] [8] [4] [4] OaIE*EAE/0 [3] OaIE*EAE/0 [2] [1] OaIE*EAE/2 AxO1/4OO/ AEao*xAE// AAEo/ IO. O O 1 = Start for Timer 2 1 = Interval mode (auto reload) 1 = Inverter on for TOUT1 OaIE*EAE/1 OaIE*EAE/1 OaIE*dead zone AxO1/4OO/ AEao*xAE// 1 = Inverter on for TOUT0 OaIE*EAE/0 OaIE*EAE/0 AEOuA 1 = Update TCNTB0TCMPB0 AAEo/ IO. AEOuA 1 = Update TCNTB1TCMPB1 AAEo/ AUx/. O O IO. 0 = One-shot 0 = Inverter off 0 = No operation 1 = Start for Timer 1 0 = Disable 1 = Enable 0 = One-shot 0 = Inverter off 0 = No operation 1 = Interval mode (auto reload) 1 = Start for Timer 0 R/W R/W EAE/0 EAE/1 EAE/1 EAE/1 EAE/2 EAE/2 EAE/2 EAE/3 EAE/3 EAE/3 EAE/4 EAE/4 E1/2Ia1/4AaeAE/ 1/4AEEyUiAae/ 1/4AEEyaAae/ oE1/4O 1/4AEEyUiAae/ 1/4AEEyaAae/ E1/2Ia1/4AaeAE/ oE1/4O oE1/4O 1/4AEEyUiAae/ 1/4AEEyaAae/ E1/2Ia1/4AaeAE/ oE1/4O oE1/4O oE1/4O EAE/0 EAE/0 1/4AEEyUiAae/ 1/4AEEyaAae/ E1/2Ia1/4AaeAE/ oE1/4O oE1/4O oE1/4O E1/2Ia1/4AaeAE/ oE1/4O oE1/4O oE1/4O 1/4AEEyaAae/ oE1/4O oE1/4O 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 R/W R/W R/W R/W R/W R/W R/W R/W TCNTO4 14 EAE/5 TCNTB5 15 EAE/5 TCNTO5 1/4AEEyUiAae/ 0x01D50044 1/4AEEy/ E1/2Ia1/4AaeAE/ 0x01D50048 0x01D5004C R R/W R EAE/4 EAE/5 EAE/5 1/4AEEyUiAae/ 1/4AEEyaAae/ 1/4AEEyUiAae/ oE1/4O oE1/4O oE1/4O 0x00000000 0x00000000 0x00000000 10 aCo. UART *EI1/2OEOOIa(c)EaAOA, oA1/2oIOI,5 *EIAE/OEOuYIo1/4CO(R)UEaoA-0 1/2OEOAE/EOO1/4iacoiIoaeAframe eO3/4OcoiIoOUAIAEyYAOAEA1/2iframe IOIOYIo1/4E3/4RxDn UART oA(c) AoSIO iIa*E/ 6 7 8 IEy3/4YIAEaeA1/4Ne|AUIOAuE/OOOMCLK xIEOAE1/4a iIoIOYIo1/4AEaOAOoEe iIoEC1/2OOy3/4YAA EaEeOA1/4-0 xIEOAE1/4a oxOAE1/4aAEUAO1/2Oy3/4Y (c) EOOAnRTS InCTS A1/2oxOA/OOAEU InCTS A nCTSnCTS IEE* AEOOA FIFOO EOy3/4YOU1/2O 1/4iOE3/41/2OOFIFOx1/4A1/2OEOy3/4Y(c)FIFOE I NOn1/2OEOAOIoBDMA 2 3 1/4ieOUUFSTATn OO1/2e2 (c) 2 1/4ieUMSTATn[0] EIaCoo*FIFO1/4AaeAE/ uOI1 Ec A nCTS1/4Ey3/4Y1/2*EIOAEOO i(c) iIoIOYIo1/41/2OEOFIFO/ xI1/4AaeAE/OE3/4 iIoIOYIo1/4x/1/2OEOEOyAEOICe 1/4iE FIFOO*EI1/4iOyAEOxI AE1/2OAAuEDMA AE1/2 AuxIEIE 1/2OEOOAEI1/4Aae/y3/4YAu *CFIFOAE1/2 Ceo FIFOA1/2OOyAEuxI ax1/4 1/4AaeAE/ORx FIFO OAUMCONn[0] I1 i1/4 (c) 1/4AEEyOEcuOU15OAOeEe I0 i1/4 nRTS(c) nRTSMCONn[0] EeOAU (c) *nOo A EOxOA/OAEOaOEEi1/4nRTS nRTSOOE*EIO OOAE1/2EOIo1/4 UARTxEy3/4Y(c)1/2OO1/4A 3/4Y1/2AE/EayEI* IAu1/4OOo16xO1/2UAOEOe*EIFIFO 1/2OEOIrDA 1.0 (c), OoE1/4I OOO SIOE1/2oDMA IAUx/OUOEO S3C44B0X UARTSIO U1/2(R)AEoOiIa(c)O AE1/2OIOAxio115.2kbps, OUFIFOAE1/2OOaCoFIFOIOEOUEO1/2O3 1/2OEO xOA/OOAEAFC UARTA1/2OMODEM EOOAEOUxA/ xAO*1/2AOaI OE FIFOOaOUA1/2oxOAO1/4aEnRTS OaO1/4aOUOoxO1/2IAEnRTS OU*CxA/OOAEUE 1/2OEOUx/1 S3C44B0XA UART OUUART A1/2OUART *EIUx/ 1 NOn*EIAE1/2OIoBDMA AoUART A*EIFIFO/ OcoiIoAEaeA1/4frame 1/2OEOFIFO y3/4Y1/4AaeAE/OIEIIEcuOUO EIFIFO*EIaeAE/oI1/4A1/2OEy3/4Y AE/O*EOOI I OAEoxIOciIoaeA1/4frame aIO*EIOAE1/4Aae/a(c)xIOEUART 1/2OEOFIFOAuxII*EFIFOOxIAOUDMA OIuEIo1/4xU1/2aEcA AaI RxOI FIFO 1 FIFO 2 1/2OEO Tx OI *EIFIFOOxI1/4i iIoIOYIo1/4 EuOAiIoA1/4uEOoOIEcu iIoIEoIOuEO 21/2OEOFIFO1/2iEEOcoiIo(c) AI*EIEy3/4YeE ErrorOI 1 1/4ia1/2AEaeAiIoframe UARTIFIFOIFIFOOOUFIFO1/4iIoEO1/2Oo3/4YOAE/OAyae oiIoxOO Ioxi E3/4 IoOI1/2oOU3/4OiAEyYx1/4AuE IOAE uE o16*Oo16 yOEOOOI AE/IO *OAE1/4Aae/ (UBRDIVn) Loop-back AE1/2 OUAAE1/2*EIy3/4YA1/4OOO/OAa IR (Infrared) AE1/2 S3C44B0X UARTOOiIa*E1/2OEO Ey3/4Y0 EIOUia* AoaiEOeoOUENu UART 1/4AaeAE/ 1 UARTIOOAE ULCON0 ULCON1 IAuAE Reserved Infra-Red Mode 1/4AaeAE/ 0x01D00000 0x01D04000 BIT [7] [6] AIE*ECnOiIaA1/2 0 = Normal mode operation 1 = Infra-Red Tx/Rx mode Parity Mode [5:3] AIE*AEaeA1/4cuEINe 0xx = No parity 100 = Odd parity 101 = Even parity 110 = Parity forced/checked as 1 111 = Parity forced/checked as 0 stop bit [2] AIE*IOAoEy 0 = One stop bit per frame 1 = Two stop bit per frame Word length [1:0] AIE*Ey3/4YAo 00 = 5-bits 01 = 6-bits 11 = 7-bits 11 = 8-bits 2 UARTOOAE1/4Aae/ UCON0 UCON1 IAuAE 0x01D00004 0x01D04004 BIT Tx interrupt type [9] *EIOICeoAa 0 = Pulse 1 = Level Rx interrupt type [8] 1/2OEOOICeoAaI 0 = Pulse R/W UART0OOAE1/4Aae/ AeEo oE1/4O 0x00 oE1/4O 0x00 R/W UART1OOAE1/4Aae/ R/W UART0AIOOAE R/W UART1AIOOAE AeEo 1/4AaeAE/ oE1/4O 0x00 1/4AaeAE/ oE1/4O 0x00 EA3/161/4aAaECINuAoE O1/2O IiEIAoaEC* 1/16OE o RX aeOO1 EOOIOAAE/uEI* 1/2(2 16 16IOEUART AE/AO* -1).E1/2EcIA IOAE UBRDIVn = (round_off)(MCLK/(bps x 16) ) -1. 1 = Level Rx time out enable Rx error status interrupt enable [6] OEi/ OEiUART iIoOI 0 = Do not generate receive error status interrupt 1 = Generate receive error status interrupt Loop-back Mode [5] AI1 EUART 1/2oEeloop back 0 = Normal operation 1 = Loop-back mode Send Break Signal [4] AI1 Cay 0 = Normal transmit 1 = Send break signal Transmit Mode [3:2] OaA1/2IE*AoEEOOTX Ey3/4Y1/2UART *EIO1/4AaeAE/ 00 = Disable 01 = Interrupt request or polling mode 10 = BDMA0 request (Only for UART0) 11 = BDMA1 request (Only for UART1) Receive Mode [1:0] OaA1/2IE*AoEEOOOUART 1/2OEOa1/4AaeAE/Ay3/4Y 00 = Disable, 01 = Interrupt request or polling mode 10 = BDMA0 request (Only for UART0) 11 = BDMA1 request (Only for UART1) 3 UART FIFO OOAE1/4Aae/ UFCON0 UFCON1 IAuAE 0x01D00008 0x01D04008 BIT [7:6] OaA1/2IE*EIFIFOA*Io1/4 00 = Empty 01 = 4-byte 10 = 8-byte 11 = 12-byte Rx FIFO TriggerLevel [5:4] OaA1/2IE*OEFIFOA*Io1/4 00 = 4-byte 01 = 8-byte 10 = 12-byte 11 = 16-byte Reserved Tx FIFO Reset [3] [2] TX FIFOIAOUFIFOIoxOCay 0 = Normal 1= Tx FIFO reset Rx FIFO Reset [1] Rx FIFOIAOUFIFOIoxOCay 0 = Normal 1= Rx FIFO reset FIFO Enable 4 UART MODEM OOAE1/4Aae/ UMCON0 UMCON1 0x01D0000C 0x01D0400C R/W UART0 MODEMOOAE1/4Aae/ oE1/4O 0x00 oE1/4O 0x00 R/W UART1 MODEMOOAE1/4Aae/ [0] 0 = FIFO disable 1 = FIFO mode R/W UART0 FIFOOOAE1/4Aae/ AeEo oE1/4O 0x00 oE1/4O 0x00 R/W UART1 FIFOOOAE1/4Aae/ EUART *EIOoOYIo1/4AIUAox AE1/2 [7] OEi/ OEiRx EOI 0 = Disable 1 = Enable Tx FIFO Trigger Level BIT Reserved AFC(Auto Flow Control) Reserved Request to Send [4] [3:1] [0] EcuAFC AFCEC*nOEi [7:5] OaA1/2IOe 0 AeEo 0 = Disable 1 = Enable 0 OaA1/2IOe 0 OEi, AIoAO 0 = 'H' level(Inactivate nRTS) 1 = 'L' level(Activate nRTS) 5 UART TX/RXxI1/4AaeAE/ UTRSTAT0 UTRSTAT1 IAuAE Transmit shifter Empty [2] AIOU*EIOAE1/4Aae/OEy3/4YoO I1 0 = Not empty 1 = Transmit holding & shifter register empty Transmit buffer Empty [1] AIOU*EIa1/4AaeAE/OuEy3/4Y1 Ecu UART 1/4AEEyIITx FIFO EOAFIFO, AueO3/4IIae1/4ieA OA|1/4ieUFSTAT 1/4AaeAE/Tx FIFO 0x01D00010 0x01D04010 BIT R R UART0 TX/RXxI1/4AaeAE/ UART1 TX/RXxI1/4AaeAE/ AeEo oE1/4O 0x6 oE1/4O 0x6 0 =The buffer register is not empty 1 = Empty Receive buffer data ready [0] IAUE1/2OOa1/4AaeAE/uy3/4YA1 Ecu UART 1/4AEEyIuIaeieA 0 = Completely empty 1 = The buffer register has a received data 6 UART iIoxI1/4AaeAE/ UERSTAT0 UERSTAT1 IAuAE Break Detect 0x01D00014 0x01D04014 BIT [3] AI1 R R AeEo OE3/4OoOYIAN-1/2OO 0 = No break receive 1 = Break receive Frame Error [2] AI1 OE3/4Ooframe iIo*Eu 0 = No frame error during receive 1 = Frame error Parity Error [1] AI1 OE3/4OU1/2OOOoAEaeA1/4iIo*Eu 0 = No parity error during receive UART0 iIoxI1/4AaeAE/ UART1 iIoxI1/4AaeAE/ oE1/4O 0x6 oE1/4O 0x6 EOAFIFO, OA|1/4ieUFSTAT 1/4AaeAE/Rx FIFO 1 = Parity error Overrun Error [0] AI1 OE3/4OociIo*Eu 0 = No overrun error during receive 1 = Overrun error xUART iIoxI1/4AaeAE/EUERSATn[3:0] xOCay 7 UART FIFOxI1/4AaeAE/ UFSTAT0 UFSTAT1 0x01D00018 0x01D04018 BIT [15:10] [9] *EI FIFOAuEAI1 0 = 0-byte Tx FIFO data 15-byte 1 = Full R R UART0 FIFOxI1/4AaeAE/ oE1/4O 0x6 UART1 FIFOxI1/4AaeAE/ oE1/4O 0x6 AeEo IAuAE Reserved Tx FIFO Full Rx FIFO Full [8] *EI FIFOAuEAI1 0 = 0-byte Rx FIFO data 15-byte 1 = Full Tx FIFO Count Rx FIFO Count 8 UMSTAT0 UMSTAT1 IAuAE Delta CTS [7:4] [3:0] 0x01D0001C 0x01D0401C BIT Tx FIFOAiAEy3/4YA Rx FIFOAiAEy3/4YA R R [4] oON3/4-AaxI 0 = Has not changed 1 = Has changed UART0 MODEMxI1/4AaeAE/ oE1/4O 0x6 UART1 MODEMxI1/4AaeAE/ oE1/4O 0x6 AeEo AIOE3/4aEe1/2S3C44B0X AnCTS AxOOEIIA UART MODEMxI1/4AaeAE/ Reserved Clear to Send 9 UART *EIa1/4AaeAE/FIFO1/4AaeAE/ UTXH0 UTXH1 [3:1] [0] Reserved 0 = CTS signal is not activated(nCTS pin is high) 1 = CTS signal is activated(nCTS pin is low) 0x01D00020(Little endian) 0x01D00023(Big endian) 0x01D04020(Little endian) 0x01D04023(Big endian) W(byte) W(byte) UART0*EIa1/4AaeAE/ oE1/4O UART1*EIa1/4AaeAE/ oE1/4O - 10 UART 1/2OEOa1/4AaeAE/IFIFO1/4AaeAE/ URXH0 URXH1 x: OcoiIoIOE, iIooIO. 11 UART IOAE*OAE1/4Aae/ UBRDIV0 UBRDIV1 0x01D00028 0x01D04028 R/W R/W UART0IOAE*OAE1/4Aae/ oE1/4O UART1IOAE*OAE1/4Aae/ oE1/4O 0x01D00024(Little endian) 0x01D00027(Big endian) 0x01D04024(Little endian) 0x01D04027(Big endian) URXHn,*nOo, 1/4EUSTATn A R(byte) R(byte) OcoIN3/4-Cay, UART01/2OEOa1/4AaeAE/ oE1/4O UART11/2OEOa1/4AaeAE/ oE1/4O IAOo1/2OEOAy3/4Y Oco 11 OO1/2xOAi1/4OAIoIaiEA-I 1/2*InIAOAoO|A1/4-EEA 0X18 IAARM INTERRUPT CONTROLLER (c)OUaoOICeo*EuE S3C44B0XAOIOAE/O30oOIO S3C44B0XOOAAI|AiE1/2AEIvectored interrupt mode o 0X1COOeOoEIaO II*InAOo1/2aO|oxAiEAOU AI (c) AEi1/4*1/2UooEUOIoeNOE - *OAiuAE/Ae= 0xea000000 +(( EINT2 EINT3 EINT4/5/6/7 TICK RTC INT_ZDMA0 INT_ZDMA1 INT_BDMA0 INT_BDMA1 INT_WDT INT_UERR0/1 INT_TIMER0 INT_TIMER1 INT_TIMER2 INT_TIMER3 INT_TIMER4 INT_TIMER5 INT_URXD0 INT_URXD1 INT_IIC INT_SIO INT_UTXD0 INT_UTXD1 INT_RTC INT_ADC OIOA E1/4 uE Ae OOUIRQ ISQOIO1/2OAE1/4uEAe|AiuIaoO1 masterO4 I2 OAIE1/4). I2 oIOAIE1/4O(sGKnAEaOAIE1/4OU6 Oomaster oOIOAOAE1/4mGKn IOAaOAIOIOoE1/2oAAEcu AeuEIOAE1/4oOCeoO IaOI 2 IaOI3 IaOI4/5/6/7 EAE/IOI DMA0 OI DMA1 OI CADMA0 CADMA1 AA*EAE/OI EAE/0 EAE/1 EAE/2 EAE/3 EAE/4 EAE/5 UART01/2OEOOI UART11/2OEOOI IIC OI SIO OI UART0*EIOI UART1*EIOI RTC 3/4aeOI ADC 1/2aEoOI OI OI OI OI OI OI OI mGB UART0/1iIoOI OI mGA mGA mGA mGA mGB mGB mGB mGB sGKA mGB mGC mGC mGC mGC mGC mGC mGD mGD mGD mGD mGD mGD mGKA - mGKB - sGC sGD sGKA sGKB sGA sGB sGC sGD sGKB sGA sGB sGC sGD sGKA sGKB sGA sGB sGC sGD sGKA sGKB o oslaveOAoslaveOUAi6 oOAIE1/4OOxiIAEasGKA OUAi4 AEaO4 OIOU26oOIOOAE1/4xiICOINT_RTC oslaveOmGn oslaveOAOAIE1/4IoEaIAEaO2 AOAIE1/4U I2 oOIOmGKn OAAE*4 oOIO oOIOuA4 oEaIAOAIE1/4O(sGn) AOAIE1/4UsGKB oslaveO, A INT_RTC I INT_ADC INT_ADCAOAIE1/4 OI1/4AaeAE/ 1 OIO AE1/4Aae / INTCON IAuAE V BIT [3] [2] Reserved 0x01E00000 R/W AuAE OIOAE1/4Aae/ 0x7 AIOEiIRQEOAIoAAE1/2 0 = Vectored interrupt mode 1 = Non-vectored interrupt mode I [1] AIOEiIRQOI 0 = IRQ interrupt enable 1 = Reserved :OUEOAIRQOIO(R)CAIOeay F [0] AIOEiFIQ OI 0 = FIQ interrupt enable (FIQOIOoAAE1/2) 1 = Reserved x 1 OIOAE1/4Aae / INTPND IAuAE EINT0 EINT1 EINT2 EINT3 EINT4/5/6/7 INT_TICK INT_ZDMA0 INT_ZDMA1 INT_BDMA0 INT_BDMA1 INT_WDT INT_TIMER0 INT_TIMER1 INT_TIMER2 INT_TIMER3 INT_TIMER4 INT_TIMER5 INT_URXD0 INT_URXD1 INT_IIC INT_SIO INT_UTXD0 INT_UTXD1 INT_RTC INT_ADC 3 OIAE1/21/4 aeAE/ INTMOD IAuAE EINT0 EINT1 EINT2 EINT3 EINT4/5/6/7 INT_TICK INT_ZDMA0 BIT [25] [24] [23] [22] [21] [20] [19] 0x01E00008 R/W AuAE 0 = IRQ mode 1 = FIQ mode 0 = IRQ mode 1 = FIQ mode 0 = IRQ mode 1 = FIQ mode 0 = IRQ mode 1 = FIQ mode 0 = IRQ mode 1 = FIQ mode 0 = IRQ mode 1 = FIQ mode 0 = IRQ mode 1 = FIQ mode OIAE1/21/4aeAE/ 0x0000000 BIT [25] [24] [23] [22] [21] [20] [19] [18] [17] [16] [15] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] 0x01E00004 R/W OE3/4ICeoxI AuAE 0 = Not requested, 1 = Requested 0 = Not requested, 1 = Requested 0 = Not requested, 1 = Requested 0 = Not requested, 1 = Requested 0 = Not requested, 1 = Requested 0 = Not requested, 1 = Requested 0 = Not requested, 1 = Requested 0 = Not requested, 1 = Requested 0 = Not requested, 1 = Requested 0 = Not requested, 1 = Requested 0 = Not requested, 1 = Requested 0 = Not requested, 1 = Requested 0 = Not requested, 1 = Requested 0 = Not requested, 1 = Requested 0 = Not requested, 1 = Requested 0 = Not requested, 1 = Requested 0 = Not requested, 1 = Requested 0 = Not requested, 1 = Requested 0 = Not requested, 1 = Requested 0 = Not requested, 1 = Requested 0 = Not requested, 1 = Requested 0 = Not requested, 1 = Requested 0 = Not requested, 1 = Requested 0 = Not requested, 1 = Requested 0 = Not requested, 1 = Requested 0 = Not requested, 1 = Requested 0x0000000 : OUEOAFIQ OI (R)CAIO e ay INT_UERR0/1 [14] INT_ZDMA1 INT_BDMA0 INT_BDMA1 INT_WDT INT_TIMER0 INT_TIMER1 INT_TIMER2 INT_TIMER3 INT_TIMER4 INT_TIMER5 INT_URXD0 INT_URXD1 INT_IIC INT_SIO INT_UTXD0 INT_UTXD1 INT_RTC INT_ADC 3 OIAEAI1/4Aae / [18] [17] [16] [15] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] 0 = IRQ mode 1 = FIQ mode 0 = IRQ mode 1 = FIQ mode 0 = IRQ mode 1 = FIQ mode 0 = IRQ mode 1 = FIQ mode 0 = IRQ mode 1 = FIQ mode 0 = IRQ mode 1 = FIQ mode 0 = IRQ mode 1 = FIQ mode 0 = IRQ mode 1 = FIQ mode 0 = IRQ mode 1 = FIQ mode 0 = IRQ mode 1 = FIQ mode 0 = IRQ mode 1 = FIQ mode 0 = IRQ mode 1 = FIQ mode 0 = IRQ mode 1 = FIQ mode 0 = IRQ mode 1 = FIQ mode 0 = IRQ mode 1 = FIQ mode 0 = IRQ mode 1 = FIQ mode 0 = IRQ mode 1 = FIQ mode 0 = IRQ mode 1 = FIQ mode 0 = IRQ mode 1 = FIQ mode 0x07ffffff AeEo INT_UERR0/1 [14] INTMSK 0x01E0000C R/W In*IO1/2AOAEA IAEAoOIOE*A IAuAE Global EINT0 EINT1 EINT2 EINT3 EINT4/5/6/7 INT_TICK INT_ZDMA0 INT_ZDMA1 INT_BDMA0 INT_BDMA1 INT_WDT INT_TIMER0 INT_TIMER1 INT_TIMER2 INT_TIMER3 INT_TIMER4 INT_TIMER5 INT_URXD0 INT_URXD1 BIT Reserved [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16] [15] [13] [12] [11] [10] [9] [8] [7] [6] 0 = Service available 1 = Masked 0 = Service available 1 = Masked 0 = Service available 1 = Masked 0 = Service available 1 = Masked 0 = Service available 1 = Masked 0 = Service available 1 = Masked 0 = Service available 1 = Masked 0 = Service available 1 = Masked 0 = Service available 1 = Masked 0 = Service available 1 = Masked 0 = Service available 1 = Masked 0 = Service available 1 = Masked 0 = Service available 1 = Masked 0 = Service available 1 = Masked 1 0 = Service available 1 = Masked 0 = Service available 1 = Masked 0 = Service available 1 = Masked 0 = Service available 1 = Masked 0 = Service available 1 = Masked 0 = Service available 1 = Masked 0 = Service available 1 = Masked INT_UERR0/1 [14] INT_IIC INT_SIO INT_UTXD0 INT_UTXD1 INT_RTC INT_ADC 3 1/4AaeAE/ I_PSLV I_PMST I_CSLV I_CMST I_ISPR IRQOIoAAE1/21/4aeAE/ OO* [5] [4] [3] [2] [1] [0] A 0 = Service available 1 = Masked 0 = Service available 1 = Masked 0 = Service available 1 = Masked 0 = Service available 1 = Masked 0 = Service available 1 = Masked 0 = Service available 1 = Masked / AeEo E*slavexeAIRQOAIE1/4 master1/4AaeAE/IRQOAIE1/4 Cslave1/4AaeAE/IRQOAIE1/4 Cmaster IRQOI*InOAE1/4Aae/ (IE1/2oAUO*InEeOA) 0x00000000 IRQOI*InCay1/4AaeAE/ FIQ OI*InCay1/4AaeAE/ Undef. Undef. Ee1,INTPND 1/2xOCay) 1/4AaeAE/IRQOAIE1/4 0x1b1b1b1b 0x00001f1b 0x1b1b1b1b 0x0000xx1b oE1/4O 0x01E00010 0x01E00014 0x01E00018 0x01E0001C 0x01E00020 R/W R/W R R R I_ISPC F_ISPC OUISR 1 2 I_PSLVAIAeEo IAuAE OI*InIA1/2aEoINTPNDOeCay 0x01E00024 0x01E0003C W W (OI_ISPC/ F_ISPC IAECayI_ISPC/F_ISPC, IyI_ISPC/F_ISPC O|AxnEOEcIAA1/2oaeOo OI*InIaeE 1/4AaeAE/ACayI_ISPR/INTPND1/4AaeAE/ I_ISPC/F_ISPC1/4AaeAE/1/2oUOUISR EcuxnEOOaA1/2oaeOoUOICeo*EuI_ISPR/INTPND1/4AaeAE/EOOI0 BIT [31:24] [23:16] [15:8] [7:0] BIT [31:30] [29:28] [27:26] [25:24] [23:22] [21:20] [19:18] [17:16] E*mGA AosGn PSLAVE@mGB PSLAVE@mGC PSLAVE@mGD PSLAVE@mGA sGA (EINT0) sGB (EINT1) sGC (EINT2) sGD (EINT3) PSLAVE@mGB sGA (INT_ZDMA0) sGB (INT_ZDMA1) sGC (INT_BDMA0) sGD (INT_BDMA1) PSLAVE@mGC 00: 1 st 01: 2 nd 10: 3 rd 11: 4 th 00 00: 1 st 01: 2 nd 10: 3 rd 11: 4 th 01 00: 1 st 01: 2 nd 10: 3 rd 11: 4 th 10 00: 1 st 01: 2 nd 10: 3 rd 11: 4 th 11 E*mGB AosGn E*mGC E*mGD AeEo 00: 1 st 01: 2 nd 10: 3 rd 11: 4 th 00: 1 st 01: 2 nd 10: 3 rd 11: 4 th 00: 1 st 01: 2 nd 10: 3 rd 11: 4 th 00: 1 st 01: 2 nd 10: 3 rd 11: 4 th AosGn AosGn OeOIAAIE1/4 oE1/4O 00 01 10 11 OeOIAAIE1/4 OAsGA, B, C, D OeOIAAIE1/4 OAsGA, B, C, D OeOIAAIE1/4 AOAIE1/4 OAsGA, B, C, D AOAIE1/4 AOAIE1/4 AeEo OAsGA, B, C, D AOAIE1/4 PSLAVE@mGA sGA (TIMER0) sGB (TIMER1) sGC (TIMER2) sGD (TIMER3) PSLAVE@mGD sGA (INT_URXD0) sGB (INT_URXD1) Sgc (INT_IIC) sGD (INT_SIO) xI_PSLAVEAIiOeAaOAIOE1/4EOUa|CeoA [15:14] [13:12] [11:10] [9:8] [7:6] [5:4] [3:2] [1:0] 00: 1 st 01: 2 nd 10: 3 rd 11: 4 th 00 00: 1 st 01: 2 nd 10: 3 rd 11: 4 th 01 00: 1 st 01: 2 nd 10: 3 rd 11: 4 th 10 00: 1 st 01: 2 nd 10: 3 rd 11: 4 th 11 00: 1 st 01: 2 nd 10: 3 rd 11: 4 th 00 00: 1 st 01: 2 nd 10: 3 rd 11: 4 th 01 00: 1 st 01: 2 nd 10: 3 rd 11: 4 th 00: 1 st 01: 2 nd 10: 3 rd 11: 4 th 10 11 I_PMST1/4AaeAE/IAeEo IAuAE Reserved M FxSLV[A:D] PMASTER FxSLV Fx@mGA Fx@mGB Fx@mGC Fx@mGD PMASTER mGA mGB mGC mGD xI_PMST AIiOeAaOAIOE1/4EOUa|CeoA BIT [15:13] [12] [11:8] [7:0] [11] [10] [9] [8] [7:6] [5:4] [3:2] [1:0] AeEo Master Ux/AE1/2 0 = round robin 1 = fix mode SlaveUx/AE1/2 0 = round robin 1 = fix mode E*4 oslaveOAOAIE1/4 AUx/E1/2 AUx/E1/2 AUx/E1/2 AUx/E1/2 E*slaveO @mGA E*slaveO @mGB E*slaveO @mGC E*slaveO @mGD 00: 1 st 01: 2 nd 10: 3 rd 11: 4 th 00: 1 st 01: 2 nd 10: 3 rd 11: 4 th 00: 1 st 01: 2 nd 10: 3 rd 11: 4 th 00: 1 st 01: 2 nd 10: 3 rd 11: 4 th I_CSLV1/4AaeAE/IAeEo IAuAE BIT AeEo OAsGA, B, C, D OAsGA, B, C, D OAsGA, B, C, D OAsGA, B, C, D ACOAIE1/4 ACOAIE1/4 ACOAIE1/4 ACOAIE1/4 0x1b 0x1b 0x1b 0x1b 00 01 10 11 00 01 10 oE1/4O CSLAVE@mGA [31:24] OE3/4mGA CSLAVE@mGB [23:16] OE3/4mGB CSLAVE@mGC [15:8] OE3/4mGC CSLAVE@mGD [7:0] CSLAVE@mGA sGA (EINT0) sGB (EINT1) sGC (EINT2) sGD (EINT3) [31:30] [29:28] [27:26] [25:24] 00: 1st 01: 2nd 10: 3rd 11: 4th 00: 1st 01: 2nd 10: 3rd 11: 4 th OE3/4mGD 00: 1st 01: 2nd 10: 3rd 11: 4th 00: 1st 01: 2nd 10: 3rd 11: 4th 00: 1 st 01: 2 nd 10: 3 rd 11: 4 th 00: 1 st 01: 2 nd 10: 3 rd 11: 4 th 00: 1 st 01: 2 nd 10: 3 rd 11: 4 th CSLAVE@mGB sGA (INT_ZDMA0) [23:22] sGB (INT_ZDMA1) [21:20] sGC (INT_BDMA0) [19:18] sGD (INT_BDMA1) [17:16] CSLAVE@mGC sGA (TIMER0) sGB (TIMER1) sGC (TIMER2) sGD (TIMER3) CSLAVE@mGD sGA (INT_URXD0) [7:6] sGB (INT_URXD1) [5:4] sGC (INT_IIC) sGD (INT_SIO) I_CMST1/4AaeAE/IAeEo IAuAE Reserved VECTOR CMASTER CMASTER mGA mGB mGC mGD I_ISPR1/4AaeAE/IAeEo IAuAE EINT0 EINT1 EINT2 EINT3 INT_TICK BIT [25] [24] [23] [22] [20] [7:6] [5:4] [3:2] [1:0] BIT [15:14] [13:8] [7:0] [3:2] [1:0] [15:14] [13:12] [11:10] [9:8] 00: 1 st 01: 2 nd 10: 3 rd 11: 4 th 00: 1 st 01: 2 nd 10: 3 rd 11: 4 th 00: 1 st 01: 2 nd 10: 3 rd 11: 4 th 00: 1 st 01: 2 nd 10: 3 rd 11: 4 th 00: 1 st 01: 2 nd 10: 3 rd 11: 4 th 00: 1 st 01: 2 nd 10: 3 rd 11: 4 th 00: 1 st 01: 2 nd 10: 3 rd 11: 4 t h 00: 1 st 01: 2 nd 10: 3 rd 11: 4 th 00: 1 st 01: 2 nd 10: 3 rd 11: 4 th AeEo OO|*OuAE/AeAI6 masterACOAIE1/4 I 00011011 11 00 01 10 11 00 01 10 11 oE1/4O 0 unknown 00: 1 st 01: 2nd 10: 3rd 11: 4th 00 00: 1 st 01: 2nd 10: 3rd 11: 4th 01 00: 1 st 01: 2nd 10: 3rd 11: 4th 10 00: 1 st 01: 2nd 10: 3rd 11: 4th 11 AeEo oE1/4O 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = not serviced 1 = serviced now 0 = not serviced 1 = serviced now 0 = not serviced 1 = serviced now 0 = not serviced 1 = serviced now 0 = not serviced 1 = serviced now 0 = not serviced 1 = serviced now 0 = not serviced 1 = serviced now 0 = not serviced 1 = serviced now 0 = not serviced 1 = serviced now 0 = not serviced 1 = serviced now 0 = not serviced 1 = serviced now 0 = not serviced 1 = serviced now 0 = not serviced 1 = serviced now 0 = not serviced 1 = serviced now 0 = not serviced 1 = serviced now 0 = not serviced 1 = serviced now 0 = not serviced 1 = serviced now 0 = not serviced 1 = serviced now 0 = not serviced 1 = serviced now 0 = not serviced 1 = serviced now 0 = not serviced 1 = serviced now EINT4/5/6/7 [21] INT_ZDMA0 [19] INT_ZDMA1 [18] INT_BDMA0 [17] INT_BDMA1 [16] INT_WDT [15] INT_UERR0/1 [14] INT_TIMER0 [13] INT_TIMER1 [12] INT_TIMER2 [11] INT_TIMER3 [10] INT_TIMER4 [9] INT_TIMER5 [8] INT_URXD0 [7] INT_URXD1 [6] INT_IIC [5] INT_SIO [4] 0 = not serviced 1 = serviced now 0 = not serviced 1 = serviced now 0 = not serviced 1 = serviced now 0 = not serviced 1 = serviced now 0 = not serviced 1 = serviced now AeEo oE1/4O 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INT_UTXD0 [3] INT_UTXD1 [2] INT_RTC INT_ADC IAuAE EINT0 EINT1 EINT2 EINT3 INT_TICK BIT [25] [24] [23] [22] [20] [1] [0] I_ISPC/F_ISPC1/4AaeAE/IAeEo 0 = No change 1 = clear the pending bit 0 = No change 1 = clear the pending bit 0 = No change 1 = clear the pending bit 0 = No change 1 = clear the pending bit 0 = No change 1 = clear the pending bit 0 = No change 1 = clear the pending bit 0 = No change 1 = clear the pending bit 0 = No change 1 = clear the pending bit 0 = No change 1 = clear the pending bit 0 = No change 1 = clear the pending bit 0 = No change 1 = clear the pending bit 0 = No change 1 = clear the pending bit 0 = No change 1 = clear the pending bit 0 = No change 1 = clear the pending bit 0 = No change 1 = clear the pending bit 0 = No change 1 = clear the pending bit 0 = No change 1 = clear the pending bit 0 = No change 1 = clear the pending bit 0 = No change 1 = clear the pending bit 0 = No change 1 = clear the pending bit 0 = No change 1 = clear the pending bit 0 = No change 1 = clear the pending bit 0 = No change 1 = clear the pending bit 0 = No change 1 = clear the pending bit 0 = No change 1 = clear the pending bit 0 = No change 1 = clear the pending bit EINT4/5/6/7 [21] INT_ZDMA0 [19] INT_ZDMA1 [18] INT_BDMA0 [17] INT_BDMA1 [16] INT_WDT [15] INT_UERR0/1 [14] INT_TIMER0 [13] INT_TIMER1 [12] INT_TIMER2 [11] INT_TIMER3 [10] INT_TIMER4 [9] INT_TIMER5 [8] INT_URXD0 INT_URXD1 INT_IIC INT_SIO INT_UTXD0 INT_UTXD1 INT_RTC INT_ADC [7] [6] [5] [4] [3] [2] [1] [0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12 uEOeALCD LCD OOAE/ I1/4IoEy3/4Ya1/2LCD OOAEA EIA4 I(c)IOE3/4OAUOeELCD E(c)IEy LCDO O3/4iOAAuoAAEAIOEEc1280*1280 4IEEAe 4IEAe (c) 8IALCD EAe A1/2OUOxio256 1/4OEo EAa8 CyAE/ LCD OOAE/OAANIOUIIaeAEaCoLCD LCD OOAE/EOA1/4aEa*IUA1/2OUOxLCD aO1/4A1/2I(c)161/4OEoaO1/44 I(c)AIOE3/4 AEAIEUo1/2OU 3/4YIiE IOE3/4AE/OE(R)1/2/ LCDIOE3/4yYA/EcIA LCD OOAE/EOOaIIE(R)1/2aEy640x480, 320x240, 160x160 LCDCDMA LCD LCDCE3/4(c)AE/IOy OAI*EaA1/2OIOE4 cEC24oxO12oFIFOL EOA(c). OEIOE3/4 OE1 E3/4OU4 EE8 OOIEI3/44 eOOiEeU1/4EC32I*OE8 A1/4EeOOiEeUI16IOEBLUEVAL[15:0] OU32IONOExeIOn8 LCDxE1/2AAOE IECAOAEaEuAOaEcOUAi1/2EOoeSL_IDLE LCD1/4AaeAE/ 1 IAuAE LINECNT(OA) CLKVAL LCDOOAE1/4Aae/1 LCDCON1 IIOE3/4A1/23 oA1/4EIAExioOE3/4256 41/4OEiU16 OO1/2OAe3/4AEI AO xOADMA FIFO OEo*OIaeCo OAAOUCPU oxOOUEaAE1/4iUIOEAFIFO IOeACeoIAxOEaOaeAE/y3/4Y1/2 LCDCDMAC3/4YAE/OEEyaeeCoOO aeCoxUA OAAOEEeOUAE1/2oO12oFIFOH OOAe IOE3/4ENnEA1/4OEU OE 2OEBLUEVAL[11:8] OE3 OiE3/4 0OEBLUEVAL[3:0] OiE3/4 OEBLUEVAL[15:12]Oi oiEOe8 EiAIA*OEOAIAeOOi oAIE2 GREENVAL[31:0] 1/4AaeAE/OE3/4 xeO3/4IECEiAIEO E1/2oIOE3/4 OaEVCLK AOIuO1/4oEUc E1/2xOEAA AE1/2 II VDO IAE E 12oFIFOH aeAE/BULEVAL[15:0] o1/4AiOAOeOAEIE OEBLUEVAL[7:4]OOE iE3/4 1/4OEIOE3/4A1/2OAeOi I*OAai3 IAIEOOIEI3/48 xe(c)*OOEREDVAL[31:0] 1/4AaeAE/OE3/4*E4 E1/2oIOE3/4A1/4OU16IONOExeIOn4 S3C44B0XOOLCD 0x01F00000 BIT [31:22] [21:12] R/W Oa(c)I*O1/4AEEyO Oa(c)IE*VCLK OOEOA. LCDOOAE1/4Aae/1 AeEo AAEAE. oE1/4O 0x00000000 EcuAOOUENVID=1 Aa, 1/2IA E1/2I WLH WDLY MMODE DISMODE [11:10] [9:8] [7] [6:5] Oa(c)INOnIE3/4A1/2 Oa(c)IE*VLINE Oa(c)IE*VLINE OaIE*VM VCLK = MCLK / (CLKVAL x 2) ( CLKVAL 2 ) cAE1/2AiE IVCLK O(R)1/4aANOE AaEUE. 00 = 4 clock, 01 = 8 clock, 10 = 12 clock, 11 = 16 clock 00 = 4clock, 01 = 8 clock, 10 = 12 clock, 11 = 16 clock 0 = Each Frame, 1 = The rate defined by the MVAL 00 = 4-bit dual scan display mode 01 = 4-bit single scan display mode 10 = 8-bit single scan display mode 11 = Not used INVCLK [4] AIOOAEVCLK A1/4O 0 = The video data is fetched at VCLK falling edge 1 = The video data is fetched at VCLK rising edge INVLINE INVFRAME INVVD [3] [2] [1] AIOE3/4AoaA1/4O 0 = normal 1 = inverted AIOE3/4(VD[7:0]) 0 = Normal A1/4O. AIOE3/4AoaA1/4O 0 = normal 1 = inverted 1 = VD[7:0] output is inverted. ENVID [0] LCDEOAEEaoIA1/4-AOie*n 0 = OEi,LCD FIFO 1 = OEi 2 IAuAE LINEBLANK HOZVAL LCDOOAE1/4Aae/1 0x01F00004 BIT R/W LCDOOAE1/4Aae/2 AeEo [31:21] Oa(c)IE*EAeAOE1/4a. LINEBLANK I Ec: LINEBLANK [20:10] Oa(c)IE*LCD AxO1/2UEyC2 IOu15oxO1/2U, 1/2LCD CyAE/*Au. AEy I10, *OE1/4aOU10oIIEOOAEU1/4aaEeVCLK OAE*OeAuxaOU aALCD EOOO(16oxO1/2U), AE(R)AE1/2cX=120 iIaA8 O, a Oo Ec120 AEAAE(R)1/2c,HOZVAL oX=128 AIECMCLK. oE1/4O 0x00000000 LCDCON2 Cay E1/2 EEA1/2 : HOZVAL = ( Horizontal display size / Number of the valid VD data line) -1 : Horizontal display size = 3 * Number of Horizontal Pixel LINEVAL E*E1/2: LINEVAL = (Vertical display size) -1:EAeAaI [9:0] Oa(c)IE*LCD AEAAOc LINEVAL = (Vertical display size / 2) -1: EEAeAaI 3 IAuAE Reserved SELFREF LCDOOAE1/4Aae/3 0x01F00040 R/W BIT [2:1] [0] Ao LCDEAAE1/2OiI 0 : LCD self refresh mode disable 1 : LCD self refresh mode enable 4 IAuAE MODESEL OaCoE1/4O *1 0x01F00008 BIT [28:27] Oa(c)INOnIE3/4A1/2 00 = monochrome mode 01 = 4-level gray mode 10 = 16-level gray mode 11 = color mode LCDBANK [26:21] Oa(c)IOE3/4OAEaCoOUIIae/AO*A[27:22] LCDBANKOUEOaOAEAUa, LCD OAEe, LCDBASEU x:1 LCDBANK 5 IAuAE OaCoE1/4O *2 0x01F0000C BIT R/W AeEo OaCoE1/4O*2 1/4AaeAE/ oE1/4O 0x000000 OU [20:0] ENVID=1EAUa. LCDCON3 LCDOOAE1/4Aae/3 oE1/4O 0x00 AeEo LCDSADDR1 R/W AeEo OaCoE1/4O*1 1/4AaeAE/ oE1/4O 0x000000 OaCoO|e4M EAEIOaCo1/4O* CoOo OoEOU*OAaaeCoO|xa Oa(c)IOE3/4aCooOUEEAeLCD A[21:1] 2 EcuLCDBASEU,LCDBASEL OU ENVID=1Ea, AAA1/2OUIO OAEx/OA, LCDSADDR2 BSWP [29] xO1/2UOAEI 1 : Swap Enable 0 : Swap Disable LCD DMA OO4 AE1/2IBSWP = 0, IoIOE3/4 *nOoBSWP =1 EcuCPU BSWP OeI0 Io4n-th, 4n+1th,4n+2th, 4n+3th. AE1/2, OaeCoEOOx1/2UEAE, AE1/2OyIO3/4, AOOEAEUEa EAIAOaeCo1/4O* A[21:1] *nOo OUlittle endian oxOAI*E1/2OEaeCoy3/4Y, OaeCoEy3/4YOOn+3th, 4n+2th ,4n+1th ,4n-th OUlittle endian OoIBSWP =1,aeEAEy3/4YO1/2OUlittle endian MVAL LCDBASEL [28:21] E1/2I: [20:0] OaA1/2IOE3/4OUOAEEeLCD E1/2EcIA: EcuMMODE=1, OaA1/2IOaVM VM Rate = VLINE Rate / ( 2 * MVAL) LCDBASEL =LCDBASEU + (PAGEWIDTH + OFFSIZE) x (LINEVAL +1) x: OAIyAa I LCDBASEL AO, LCDBASEU I LCDBASEL AOAoAEA, OoIOEIA OU O1/2aEo, AUa OE o, IOAO, EIOa LCDBASEU OAEy3/4YOAIEUa, LINECNT,OAEAI, IO| AOEUI., EcuOaEAaO, *nOoEcuUALINECNT AEy3/4Y1/2I E*. OyI1/2IOE3/4 OoIISR IAE1/4ie AO,LINECNT 6 IAuAE OaCoE1/4O *3 0x01F00010 BIT [19:9] [8:0] eAaAEAO( xOIAAIOE3/4OEe(R)1/4aaA eAaAEAiE( Ea. LCDSADDR3 OFFSIZE PAGEWIDTH x: 7 IAuAE iEeOOi1/4AaeAE/ R/W AeEo eAaAEAOO*EeA oE1/4O 0x000000 exOAEyA), exOAEyA), AOOaAUiCoOoiE AOOaCIOE3/4Axioe PAGEWIDTH I OFFSIZE OeOUENVID = 0 REDLUT BIT REDVAL 0x01F00014 [31:0 ] Oa(c)IOa8 R/W iEeOOi1/4AaeAE/ oE1/4O 0x00000000 AeEo xeAAOO16oOEaAO1/2NOn 000 = REDVAL[3:0], 001 = REDVAL[7:4] 010 = REDVAL[11:8], 011 = REDVAL[15:12] 100 = REDVAL[19:16], 101 = REDVAL[23:20] 110 = REDVAL[27:24], 111 = REDVAL[31:28] 8 IAuAE AIEeOOi1/4AaeAE/ GREENLUT BIT GREENVAL 0x01F00018 [31:0 ] Oa(c)IOa8 R/W AIEeOOi1/4AaeAE/ oE1/4O 0x00000000 xeAAOO16oOEaAO1/2NOn AeEo 000 = GREENVAL[3:0], 001 = GREENVAL[7:4] 010 = GREENVAL[11:8], 011 = GREENVAL[15:12] 100 = GREENVAL[19:16], 101 = GREENVAL[23:20] 110 = GREENVAL[27:24], 111 = GREENVAL[31:28] 9 IAuAE AEeOOi1/4AaeAE/ BLUELUT 0x01F0001C BIT R/W AEeOOi1/4AaeAE/ oE1/4O 0x0000 AeEo BLUEVAL [15:0 ] Oa(c)IOa4 xeAAOO16oOEaAO1/2NOn 00 = BLUEVAL[3:0], 01 = BLUEVAL[7:4] 10 = BLUEVAL[11:8], 11 = BLUEVAL[15:12] 10 AE1/21/4aeAE/ DP1_2 DP4_7 DP3_5 DP2_3 DP5_7 DP3_4 DP4_5 DP6_7 0x01F00020 0x01F00024 0x01F00028 0x01F0002C 0x01F00030 0x01F00034 0x01F00038 0x01F0003C R/W AE1/2 AE1/2 AE1/2 AE1/2 AE1/2 AE1/2 AE1/2 AE1/2 AE1/21/4aeAE/ O1/4EI O1/4EI4/7 O1/4EI3/5 1/21/4AaeAE/ 1/4AaeAE/ 1/4AaeAE/ 1/4AaeAE/ 5/71/4AaeAE/ oE1/4O 0xa5a5 oE1/4O 0xba5da65 oE1/4O 0xa5a5f oE1/4O 0xd6b oE1/4O0xeb7b5ed 1/4AaeAE/ 1/4AaeAE/ 1/4AaeAE/ R/W R/W R/W R/W R/W R/W R/W R/W O1/4EI2/3 O1/4EI O1/4EI3/4 O1/4EI4/5 O1/4EI6/7 oE1/4O 0x7dbe oE1/4O 0x7ebdf oE1/4O 0x7fdfbfe oE1/4O 0x00000 DITHMODE 0x01F00044 LCDOOAE/AVCLK VCLKAEUEO|oUEy3/4YaA. Ey3/4YaEUA=HS HS: LCD E(R)AE1/2c VS: LCD Oc FR: OEUAE MV: OEIOE3/4A1/2E*O xioAEAEC16.5MHZ( OAOeAaOI0x12210. OUIIEOOI66MHZ E), VCLK(Hz)=MCLK/(CLKVAL x 2) x VS x FR x MV FR(Hz) = 1 / [ ( (1/VCLK) x (HOZVAL+1)+(1/MCLK) x (WLH+WDLY+LINEBLANK) ) x ( LINEVAL+1) ] VCLK(Hz) = (HOZVAL+1) / [ (1 /(FR x (LINEVAL+1))) - ((WLH+WDLY+LINEBLANK) / MCLK )] IOE3/4A1/2 E, 4 E, 8 41/4OE, 4 41/4OE,8 161/4OE,4 161/4OE,8 EE, 4 EE, 8 IEAe IEAeo4 IEEAe IEAe IEAeo4 IEAe IEAeo4 IEAe IEAeo4 IEEAe IEEAe IEEAe MV 1/4 1/8 1/4 1/8 1/4 1/8 3/4 3/8 OUI*4 cILCDBASEU AAE*, xOaeEAE1/2, E1/2I; xiI4 IOeEIu. O LCDBASEU1/4AaeAE/AECOao1/4O*, LCDBASEL1/4AaeAE/AOELCD LCDBASEL = LCDBASEU + LCDBASEL offset 13 A/D xAE/ S3C44B0XA1 o1/2uEAE1/4Aae/IOoEa. IOO/EcIA: xioEUAE:100KSPS EaEecN*I:0-2.5V IA/D xAE/uOo8 A*AaEaEeiIAE/, xOe0 E1/2IAE/, EOO*EuAE/,10 IA : 0-100 Hz( IAcOIu A/D xAE/1/4Aae 1 A/D xAE/OO1/4Aae ADCCON IENuIOcA*) 0x01D40000 (Li/W, Li/HW,Li/B, Bi/W) 0x01D40002(Bi/HW) 0x01D40003(Bi/B) R/W A/DxAE/OO1/4Aae oE1/4O 0x20 IAuAE FLAG BIT [6] A/DxxIeO3/4( AeEo OA) 0 = A/D conversion in process 1 = End of A/D conversion SLEEP [5] IIEcA1/2 0 = Normal operation, 1 = Sleep mode EaEeONn 000 = AIN0 001 = AIN1 010 = AIN2 011 = AIN3 100 = AIN4 101 = AIN5 110 = AIN6 111 = AIN7 INPUT SELECT [4:2] READ_ START [1] A/DxIyAAEo 0 = Disable start by read operation 1 = Enable start by read operation ENABLE_START [0] A/DxOEOEiAAEo Ecu READ_START 0 = No operation 1 = A/D conversion starts and this bit is cleared after the start-up. OEiAI. x:(Li/B/HW/W): iE3/4endian AE1/2C, AE1/2Co, Iychar/halfword/word Iychar/halfword/word IaeE IaeE (Bi/B/HW/W):. iE3/4endian 2 A/D xAE/Oe1/4Aae ADCPSR 0x01D40004 (Li/W, Li/HW,Li/B, Bi/W) 0x01D40006(Bi/HW) 0x01D40007(Bi/B) IAuAE BIT PRESCALER [7:0] AeEo OeAE/AO (0-255) Division factor = 2 (prescaler_value+1). Total clocks for ADC converstion = 2*(Prescalser_value+1)*16 3 A/D xAE/Ey3/4Y1/4Aae ADCDAT 0x01D40008 (Li/W, Li/HW, Bi/W) 0x01D4000A(Bi/HW) R/W A/DxAE/Ey3/4Y1/4Aae oE1/4O R/W A/DxAE/Oe1/4Aae oE1/4O 0x0 14 RTC (REAL TIME CLOCK) RTC (Real Time Clock)OAUUIIcE, STRB/LDRBOAiEa OAOoIa32.768 A3/4IaOUO|. 8I BCDECPU, 1/2Y3/4y OAIAe Ii E Ae *O AEuy3/4Y Iy*YcOA(c),RTC AUIyARM A RTCE : EOAu|AU OEoAe 1/2a3/4oAE2000 AAA(c)c OAAeIE1/4aIx/RTOS 3/4|AU RTC1/4AaeAE/ 1 RTCOOAE1/4Aae/ RTCCON IAuAE CLKRST CNTSEL BIT [3] [2] RTC EOO1/4AEyI 0 = No reset, 1 = Reset BCD1/4AEEyI 0 = Merge BCD counters 1 = Ao (Separate BCD counters) CLKSEL [1] BCD EOONOn 0 = XTAL 1/2 15 divided clock 1 = Reserved (XTAL clock only for test) RTCEN [0] RTCAOEi 0 = Disable, 1 = Enable 0x01D70040(little endian) 0x01D70043(Big endian) AeEo R/W(xO1/2U) RTC control Register oE1/4O 0x0 EAE1/4aI AeIEIa EcuRTC AOEi, STOP cA/1/2oOo, IAE1/4oEUSTOP I0, EaEI0, RTCEOOEOE. 2 RTC3/4OOAE1/4Aae/ RTCALM 0x01D70050(little endian) R/W(xO1/2U) RTC 0x01D70053(Big endian) IAuAE BIT AeEo Reserved [7] ALMEN [6] AlarmE3/4OOEi 0 = Disable, 1 = Enable YEAREN [5] Aealarm OEi 0 = Disable, 1 = Enable MONREN [4] OAalarm OEi 0 = Disable, 1 = Enable DAYEN [3] Iialarm OEi 0 = Disable, 1 = Enable HOUREN [2] Ealarm OEi 0 = Disable, 1 = Enable MINEN [1] *Oalarm OEi 0 = Disable, 1 = Enable SECEN [0] Aealarm OEi 0 = Disable, 1 = Enable 3 3/4AeEy Y1/4AaeAE/ 3/4OOAE1/4Aae/ cA/, aeERTCE, EeOA oE1/4O 0x0 ALMSEC IAuAE BIT 0x01D70054(little endian) 0x01D70057(Big endian) AeEo [7] [6:4] [3:0] AeABCD 0--9 Ao O (0--5) R/W(xO1/2U) AeEy3/4Y1/4AaeAE/ oE1/4O 0x00 Reserved SECDATA 4 3/4*O OEy Y1/4AaeAE/ ALMMIN IAuAE BIT 0x01D70058(little endian) 0x01D7005B(Big endian) AeEo [7] [6:4] [3:0] *OOABCD 0--9 Ao O (0--5) R/W(xO1/2U) *OOEy3/4Y1/4AaeAE/ oE1/4O 0x00 Reserved MINDATA 4 3/4E y Y1/4AaeAE/ ALMHOUR IAuAE BIT 0x01D7005C(little endian) 0x01D7005F(Big endian) AeEo [7:6] [5:4] [3:0] EABCD 0--9 Ao O (0--2) R/W(xO1/2U) Ey3/4Y1/4AaeAE/ oE1/4O 0x00 Reserved HOURDATA 5 3/4EOEy Y1/4AaeAE/ ALMDAY IAuAE BIT 0x01D70060(little endian) 0x01D70063(Big endian) AeEo [7:6] [5:4] [3:0] EOABCD 0--9 Ao O (0--3) R/W(xO1/2U) EOEy3/4Y1/4AaeAE/ oE1/4O 0x01 Reserved DAYDATA 6 3/4OAEy Y1/4AaeAE/ ALMMON IAuAE BIT 0x01D70064(little endian) 0x01D70067(Big endian) AeEo [7:5] [4] [3:0] OAABCD 0--9 Ao O (0--1) R/W(xO1/2U) OAEy3/4Y1/4AaeAE/ oE1/4O 0x01 Reserved MONDATA 7 3/4AeEy Y1/4 aeAE/ ALMYEAR IAuAE BIT 0x01D70068(little endian) 0x01D7006B(Big endian) AeEo [7:0] AeBCD O (00--99) R/W(xO1/2U) AeEy3/4Y1/4aeAE/ oE1/4O 0x00 YEARDATA RTCRST IAuAE BIT 8 RTC ROUNDI1/4AaeAE/ 0x01D7006C(little endian) 0x01D7006F(Big endian) AeEo [3] Round AeIOEi SRSTEN R/W(xO1/2U) RTC ROUNDI1/4AaeAE/ oE1/4O 0x00 0 = Disable, 1 = Enable SECCR [2:0] uEAe1/2oIARound 1/2c 011 = over than 30 sec 100 = over than 40 sec 101 = over than 50 sec 9 BCDAeEy3/4Y1/4AaeAE/ BCDSEC IAuAE BIT [7] [6:4] [3:0] 10 BCD*OOEy3/4Y1/4AaeAE/ BCDMIN IAuAE BIT [7] [6:4] [3:0] 11 BCDEy3/4Y1/4AaeAE/ BCDHOUR IAuAE BIT [7:6] [5:4] [3:0] 12 BCDEOEy3/4Y1/4AaeAE/ BCDDAY IAuAE BIT [7:6] [5:4] [3:0] 13 BCDCAEUEy3/4Y1/4Aae/ BCDDATE IAuAE BIT [7:3] [2:0] EOABCD 0x01D70080(little endian) 0x01D70083(Big endian) AeEo Ao O (1--7) Reserved DATEDATA 14 BCDOAEy3/4Y1/4AaeAE/ BCDMON IAuAE BIT [7:5] 0x01D70084(little endian) 0x01D70087(Big endian) AeEo Ao Reserved R/W(xO1/2U) BCDOAEy3/4Y1/4AaeAE/ oE1/4O Undef. R/W(xO1/2U) BCDCAEUEy3/4Y1/4Aae/ oE1/4O Undef. EOABCD 0--9 0x01D7007C(little endian) 0x01D7007F(Big endian) AeEo Ao O (0--3) Reserved DAYDATA R/W(xO1/2U) BCDEOEy3/4Y1/4AaeAE/ oE1/4O Undef. EABCD 0--9 0x01D70078(little endian) 0x01D7007B(Big endian) AeEo Ao O (0--2) Reserved HOURDATA R/W(xO1/2U) BCDEy3/4Y1/4AaeAE/ oE1/4O Undef. *OOABCD 0--9 Ao O (0--5) 0x01D70074(little endian) 0x01D70077(Big endian) AeEo Reserved MINDATA R/W(xO1/2U) BCD*3/4Y1/4AaeAE/EyOO oE1/4O Undef. AeABCD 0--9 Ao O (0--5) 0x01D70070(little endian) 0x01D70073(Big endian) AeEo Reserved SECDATA R/W(xO1/2U) BCDAeEy3/4Y1/4AaeAE/ oE1/4O Undef. MONDATA 15 BCDAeEy3/4Y1/4AaeAE/ BCDYEAR IAuAE 16 E1/4aIAEyAae/ TICNT IAuAE BIT [4] [3:0] OAABCD 0--9 O (0--1) 0x01D70088(little endian) 0x01D7008B(Big endian) AeEo [7:0] AeBCD O (00--99) R/W(xO1/2U) BCDAeEy3/4Y1/4AaeAE/ oE1/4O Undef. YEARDATA 0x01D7008C(little endian) 0x01D7008F(Big endian) BIT [7] E1/4aIOIOi 0 = disable 1 = enable E1/4aIAEyO. (1-127) AeEo R/W(xO1/2U) E1/4aIAEyAae/ oE1/4O 0x00 TICK INT ENABLE TICK TIME COUNT [6:0] Oao1/4AEEyOAUYo, OAAUAEuEO 14 WATCHDOG TIMER S3C44B0XAAA*EAE/OAOUEiIoEcIIiIoEAOOOy Ux/, IEOOUAEU. AA*EAE/OOA t_watchdog = 1/( MCLK / (Prescaler value + 1) / Division_factor ) EuOAUEOAoOy16IEAE/ACeoOI*In. AA*EAE/uEI128 oI S3C44B0XEOAEmbedded ICE AUIy AA*EAE/AIaoyU1/4i AA*EAE/1/4Aae AA*EAE/OO1/4Aae WTCON IAuAE Prescaler value Reserved watchdog timer enable/disable [5] AA*EAE/AOiI. 0x01D30000 BIT [15:8] [7:6] CPUAAE DBGACKO(c)AE1/2/OC*nUEA EAE/AA* xOeEAE/AA* /EOA1/2xU DBGACKOA R/W AeEo AA*EAE/OO1/4Aae oE1/4O 0x8021 8 O*OAE0 to (2 Ao.0 -1) 0 = Disable watchdog timer 1 = Enable watchdog timer Clock select [4:3] OaA1/2IE*EOOyOox 00: 1/16 10: 1/64 Interrupt enable/disable [2] AA*OIOEiI 0 = Disable interrupt generation 1 = Enable interrupt generation Reserved [1] AA*EaoIAOil Ao Reset enable/disable [0] 01: 1/32 11: 1/128 1:OEi 0: OEi AA*EAE/y3/4Y1/4Aae WTDAT oE1/4O0X8000 OAAaeAE/OUyCE Ey1/4AaeAE/ 1/4OOO1/2oWTCNT AA*EAE/1/4yAae WTCNT OUOIEOAOeEeO1/2o1/4 0x01D30008 R/W AA*EAE/C1/4yAae oE1/4O 0x8000 0x01D30004 R/W AA*EAE/y3/4Y1/4Aae oE1/4O 0x8000 AUEYOoE1/4Ux/UOO1/2oAE oIOOOoEUI WTDATOx1/2OA WTDATaeAA*EAE/OUUWTDAT 15 IIC-BUS 1/2OU S3C44B0XOOOoa/IIC-BUS xnEOe1/4AIIC OEcIAUx/AE1/2 O/*EIAE1/2 O/1/2OEOA O*EIAE1/2 O1/2EOA -Oe (R)I1/2OUO/S3C44B0X AU*EIo1/2OEO(R)Iy3/4YEe IIC-BUS1/2OU1/4AaeAE/ 1 IIC-BUSOOAE1/4Aae/ IICCON IAuAE Acknowledge enable [7] OU*EIAE1/2IICSDA OU1/2OEOAIICSDA Tx clock source Selection [6] IIC-busAOEOO*AE 0 = IICCLK = fMCLK /16 1 = IICCLK = fMCLK /512 Tx/Rx Interrupt Enable [5] IIC-BusTx/RxOIOEiI 0 = Disable interrupt 1 = Enable interrupt Interrupt pending flag [4] IIC-busTx/RxOIOAEeO3/4. 1 ECEAUAAI1 IOIAEUx/CayA CayOAEIo1/4IOUx/ EOIOAE IICSCL IIIIC 0 = 1) AEAOOI 2)Ee0 1 = 1) AEOIOAE 2)EIUx/ N/A IIC-buO|OEiI 1=Enable ACK generation OUACK E1/4aI*A. OUACK E1/4aII 0x01D60000 BIT R/W IIC-BUSOOAE1/4Aae/ AeEo oE1/4O 0000_XXXX Transmit clock value x1 2 3 O(R)CEe 4 Interrupt pending flag OUTx/Rx Interrupt Enable=0 I, Tx/Rx Interrupt Enable OIAE1/4oI1. R/W IIC-BUSOOAE/ AeEo [7:6] IIC-bus master/slave Tx/Rx AE1/2NOnI: 00: Slave receive mode 01: Slave transmit mode 10: Master receive mode 11: Master transmit mode Busy signal status/ START STOP Condition [5] IIC-BusA|AxII 0 = AE) IIC-bus 1 =AE) IIC-bus A| A| AuE E) IIC-bus STOP E) IIC-bus STARTAuE. IICDS EIAEy3/4YxOaUSTARTAo Serial output enable Arbitration status flag [3] IIC-busOUAyIxeO3/4I 0 = Bus arbitration successful 1 = Bus arbitration failed during serial I/O Address-as-slave status flag [2] IIC-busOOO*xIe3/4I 0 =1/4ia1/2START/STOP 1 = 1/2OEOAslaveOO*AEAaIICADD Address zero status flag [1] IIC-bus OO*I0 xIeO3/4: Cay 0 =1/4ia1/2START/STOP 1 = 1/2OEOAslaveOO*EC 00000000b Last-received bit status flag [0] IIC-busEIOI1/2OEOAxIeO3/4 0 = Last-received bit is 0 (ACK was received) 1 = Last-receive bit is 1 (ACK was not received) Cay AO [4] IIC-bus Ey3/4YaoOiI 0=Disable Rx/Tx, 1=Enable Rx/Tx xI1/4AaeAE/ oE1/4O 0000_000 E, AUOyUx/, OoE1/4EOAO Oe EEPROM1/2OUE, IIC_BUSOIoOCe 1) *EIo1/2OEOOoxOUeE 2) OOO*AEAaE 3) IAEAuxaIISDCL EIyNOO(R)CIICSDA AAEoE1/4aOCo,IICDS xUIOUAE OeOUCayIIC OIOAEI [3:0] IIC-Bus*EIOeO Tx clock = IICCLK/(IICCON[3:0]+1) OU1/2OEOAIAEuEIOIo1/4xio(R)CACK uEOOI 2 IIC-BUSOOAE/ IICSTAT IAuAE Mode selection BIT xI1/4A aeAE/ 0x01D60004 3 IIC-BUSOO*1/4AaeAE/ IICADD IAuAE Slave address 0x01D60008 BIT [7:0] R/W IIC-BUSOO*1/4AaeAE/ AeEo IICADD IICADDAOEOOUEIEoA OOO*= [7:1] Not mapped = [0] 1/2OEUy3/4YOAEI1/4Aae/ AOEOOUEIEoA oE1/4O XXXX_XXXX IOEiOIIC-bus EoaeA7 IOOO* oE1/4O XXXX_XXXX 4 IIC-BUS*EI/ IICDS 1/2OEU y3/4YOAEI1/4Aae / 0x01D6000C R/W IIC-BUS*EI/ IICSTATserial output enable = 1, IICDS IOEiIICDS 17 IIS-BUS 1/2OU S3C44B0X IIS Inter-IC Sound (c)1/2OUAUAAAOoIa8/16IAIaEuOoCODEC IISxOFIFOIa(c)DMA UI1/2OU aeE EOOO*oEO IOO/OIISnE1/2Oe MSB-justified AoIA163248fs AoIAEOO8 256384fs OO/EOIaCODEC 32xO1/2U2*16(c)A*EI1/2OEOFIFO ( OyIDMA E1/2OyaA AeO3/4I AuAeO3/4EeI1 CPU DMAA*In *EI1/2OEOAOoIOoDMA OAOyEaA1/2AiOoIA(c)DMA A IIS-BUS nE1/2 IISOEAIoI(R)Ey3/4YaEeIISDI IEOOclock(IISCLK) OO2 (R)Ey3/4Y aEU*1/2OyEIeOOANuOE OOAEyC|AiI*1/2UOOOEI E IAEy3/4Y IAOeE Y3/4yEIixIC E A A* E UOo O IxaA IEEEUAxO*EIuO1/2oO AOoaAI IEEuaAxOEI AUEeOAI0 AIAOoEOOUAEU*EIxI EOOeOU(R)3/4YOCyE NOI1/2IAEyoAAOUEOOO3/4Y*E(R)AE/ AAEIyNOEoae1/2OEOAE/uOOA*I3/4YA(c)O LRIANOnIOE3/4COy*EIAIISLRCK aeNOEoOOAEIyEAOU(R)Oao1/2 1/2eOI 1/2NOa 1/4EOOU(R)EOOAIyNOaA IISLRCKOEIO(R)UI* EuOOIOIAOAoIAUxE*AE/UECIISLRCK a 0*1/2EcuOEOEIA(c) AxOOOOI*1/2EEOECoIIE y uEIISLRCK (c)(R)Ey3/4YaoIISDO), IIISCLK AAIO/Ee xo/ OOIANOnIISLRCK (c), I(R) OOoEUAAE1/2OUCoIAEc*(c) EaA1/2*O(R)OoOoIIx/ AFIFOAE1/4aIyA*1/2IOEOOFIFOAaeEA*EI1/2OEOy3/4Y OOAE/AEIOEFIFOx1/4AeO3/4AxOCeo DMAEa*1/2EIOOFIFOAaeEODMA EaA1/2 IISoFIFOx*EIFIFOO aeAE/OOOO1/4A uEc Ey3/4YEI* OIAe1/4 1 FIFOxEIEy3/4Y*1/4A IFOIO EIF AeO3/4I Ecu OE3/4EOO1/2OOyYEoFIFOAuOoAeO3/4I0 1/2OEOFIFO Ecu0 3/4YE1/2OOy IyAeO3/4IEOOE* O/EO EOOAEaIAEA*/ AoFIFOxeOI8*exO). Io16IEy3/4Yn1/2 A(R)IEOOfs nE1/2 IENuAEAE(c) OEy3/4YI1/2OOEO*uE IAE1/2IaeOau MSB JUSTIFIED nE1/2 MSB JUSTIFIED nE1/2OeIISIAO*1/2ECEuxUIISLRCK Serial bit per channel Serial clock frequency (IISCLK) @CODECLK=256fs @CODECLK=384fs 16fs, 32fs 16fs, 32fs, 48fs 32fs 32fs, 48fs 8-bit aE*EIIAOoxOAI 16-bit IIS-BUS 1/2OU 1 IIS OOAE1/4Aae/ IISCON IAuAE index (read only) 1/4AaeAE/ 0x01D18000(Li/HW, Li/W, Bi/W) 0x01D18002(Bi/HW) BIT AeEo [8] 0 = xoIA 1 =OOIA R/W IISOOAE1/4Aae/ oE1/4O 0x100 Left/Right channel Transmit FIFO ready flag (read only) [7] 0 = *EIFIFOAOx1/4A( 1 =*EIFIFOx1/4A( Receive FIFO ready flag (read only) [6] 0 =1/2OEOFIFOAOx1/4A( 1 =1/2OEOFIFOx1/4A( Transmit DMA service request enable [5] 0 = *EIDMA 1 =*EIDMA Receive DMA service request enable Transmit channel idle Command [3] OU*EIOIxIIISLRCK Oomaster EO 0 = IISLRCK is generated. 1 = IISLRCK is not generated. Receive channel idle Command [2] OU1/2OEOIxIIISLRCK Oomaster EO 0 = IISLRCK is generated. 1 = IISLRCK is not generated. 1/4i( OYI1/2OEO) I AI1/2oOUIISEC 1/4i( OYI*E). AI1/2oOUIISEC [4] 0 = 1/2OEODMA 1 =1/2OEODMA CeoOEi CeoOEi CeoOEi CeoOEi Au) Au) O) O) IIS prescaler enable IIS interface enable (start) IIS AE1/21/4aeAE/ IISMOD IAuAE [1] 0 = OeAE/xOA 1 = OEieAE/ [0] 0 = IISOEi ( 1 = IIS OEi ( IO) AEo) 2 0x01D18004(Li/HW, Li/W, Bi/W) 0x01D18006(Bi/HW) BIT AeEo [8] 0 = MasterAE1/2 (IISLRCK 1 = SlaveAE1/2 (IISLRCK IIISCLK Eao) IIISCLK EaEe) R/W IIS AE1/21/4aeAE/ oE1/4O 0x0 Master/slave mode select Transmit/receive mode Select [7:6] 00 = Ea 01 = 10 = *EIAE1/2 11 = Active level of left/right Channel [5] 0 =IIxoA( 1 =IxoIA( Serial interface format [4] 0 = IISnE1/2 1 = MSB(Left)-justified nE1/2 Serial data bit per channel Master clock(CODECLK) frequency select (fs :ENuAEAE) Serial bit clock frequency Select [1:0] 00 = 16fs 01 = 32fs 10 = 48fs 11 = N/A [2] 0 = 256fs 1 = 384fs [3] 0 = 8-bit 1 = 16-bit IOOIA) IIOOA) 1/2OEOA *EI/ 1/2OEOA 3 IIS OeAE/1/4Aae IISPSR 0x01D18008(Li/B, Li/HW, Li/W Bi/W) 0x01D1800A(Bi/HW) 0x01D1800B(Bi/B) R/W AeEo [7:4] [3:0] eOoxO 2 4 6 OeAE/A OeAE/B AeOoxO AeOoxO IISPSR[3:0] / [7:4] 1000b 1001b 1010b eOoxO 1 - 3* clock_prescaler_A = MCLK/ IAuAE BIT Prescaler value A Prescaler value B IISPSR[3:0] / [7:4] 0000b 0001b 0010b clock_prescaler_B = MCLK/ 0011b 0100b 0101b 0110b 0111b x1 EcueOoxOI3,5,7,Z OIAAyI 8 10 12 14 16 O1/4EEC50%, 1011b 1100b 1101b 1110b 1111b cAE1/2OUUI0.5MCLK - 5* - 7* - 4 IIS FIFOOOAE1/4Aae/ IAEAEoIISUx/, 1) OEiIISFCON 2) OEiIISFCON 3) OEiIISFCON IAE1/2aEoIISUx/, OEcIAyI 1/4AaeAE/o 1/4AaeAE/FIFO 1/4AaeAE/DMA Ceo 1) OEiIISFCON OaO1/2. 2) OEiIISFCON 3) OEiIISFCON IISFCON IAuAE *EIFIFOaeEAE1/2NOn [11] 0 = OyaeEAE1/2 0x01D1800E(Bi/HW) BIT 1/4AaeAE/o 1/4AaeAE/FIFO, 1/4AaeAE/DMA Ceo EcuAaIe*EIFIFOAEOay3/4Y, Ioy 0x01D1800C(Li/HW, Li/W Bi/W) R/W AeEo IISFIFOOOAE1/4Aae/ oE1/4O x0 1 = DMA aeEAE1/2 1/2OEOFIFOaeEAE1/2NOn [10] 0 = Normal access mode 1 = DMA access mode *EIFFOOEiI [9] 0 = FIFO disable 1 = FIFO enable 1/2OEOFIFOOEiI [8] 0 = FIFO disable 1 = FIFO enable *EIFIFOEy3/4Y1/4AEEO (OA) 1/2OEOFIFOEy3/4Y1/4AEEO (OA) [3:0] Data count value = 0-8 IIS FIFO1/4AaeAE/ IISFIF *EI1/2OEOFIFOAaeEeU 0x01D18010(Li/HW) 0x01D18012(Bi/HW) R/W IIS FIFO1/4AaeAE/ oE1/4O 0x0 [7:4] Data count value = 0-8 5 18 SIO (I1/2 I/O) S3C44B0XASIO OA) *EIo1/2OEO8 SIOAe3/4OOOIA|AU 8IEy3/4Ya 12IAOeAE/ 8I1/4aoAEEy/ EOONOnA1/4(R)Ey3/4YI/O IaEOOaEe/ DMA OEAE1/2 SIOOyUx/AE1/2 *EIOe1/2EOo, AE/, EcuSIO IAEOSIO OEIEeOAI*AE1/2i, AeaI, 1) AaOAI/O 3) EeOA(R)I/O 4) EcuIe*EIEy3/4Y, 5) EeOASIOCON[3] 6) Ey3/4YOAEIUx/IeE,SIO 7) *OU4 SIO DMA Ux/ xO E AE1/2( OUAAE1/2,SIO EeOoEaIA1/4aoOUAEU. DMA*EIEy3/4Y1/2OeEcIA: 1) CaDCNTZ I0, ESIO OASIO 2) EAAaOADMA 3) SIOAaOAIDMA 4) SIOxOCeoDMA 5) SIO*EIEy3/4Y 6) *O1/2Oe4 7) EeOADCNTZ DMA1/2OEOy3/4Y1/2OeEcIA: 1) CaDCNTZ SIO 2) EAAaOADMA 3) SIOAaOAIDMA 4)EeOASIOCON[3] (SIO 5)SIOOU1/2OEO8 6)*O1/2Oe5 IEy3/4YoCeDMA O1/2DMA 1/4AEEyI0 O1/2OAE. E1/4I) AE1/41/2OOUx/ *In I0, ESIO AUCeoDMA *In. yAESIOCON[1:0] OeI00Ia, EAAaOA O1/2DMA 1/4AEEyI0 Ceo1/2oOADMA *In. I1, IOSIO *EIAE1/2. *In AUCeoDMA *In. yAESIOCON[1:0] OeI00Ia, EAAa EyO1/2*EIAE3/4YaeEeAx. *CIOEOA 1/2) OUAI8 IEy3/4Y*EIo,SIO a 1/2 2) EeOASIOCON OIOEiI Ey3/4Y1/2SIODAT. I1, E1/4y3/4YOAEIUx/ OICeoISIODAT 1/2OEOy3/4Y O|AxnEOEcIA1/2Oe: 1/2A(SIOTXD, SIOCLK, SIORXD). IEAAaOA Oo*EIEy3/4Y1/2A, Oo1/2OEOy3/4YA, OoSIO E1/4*EIy3/4Y OoxO1/2UEeSIODAT Ey3/4Y1/4Aae 1/2A((SIORXD Eao1/2A(SIOCK) ISIOTXD) I(R)Ey3/4Y. AUOe/OAaI(R)OaEe1/2U. EOOOEONnAUoIa. OaoSIO AeUOOAEAE( OE1/4AaeAE/e 7) EeOADCNTZ I1, IOSIO Ceo1/2oOADMA *In. SIO 1/2OU1/4AaeAE/ 1 SIO OOAE1/4Aae/ (SIOCON) SIOCON IAuAE 0x01D14000 R/W BIT [7] [6] [5] AI3/4oEC*nEIUx/Oi, EO1/2Ay3/4YoAO. EI1/2OEOo. *EIEy3/4Y, 3/4IEC1/2OOAyY. 0 = Receive only mode, 1 = Transmit/Receive mode Clock edge select SIO start [4] [3] OaIE*OAxo(R)EIo1/2EAOT 0 = falling edge clock, 1 = rising edge clock OaIE*SIO EC*nOEoIO AIO| '0'. BDMA Tx OA, 0 = No action 1 = Clear 3-bit counter and start shift. OaIOAEe1 Shift operation [2] E*SIO 0 = *CIOEOA1/2 ( 1 = Ao SIO mode select [1:0] E*SIO AUx/, 1/4SIODATA EcIA/ 00 = no operations 01 = SIO interrupt mode 10 = BDMA0 mode 11 = BDMA1 mode AOAEIUx/E1/2 xOEAE1/2) ACay EI ,SIO1/23/4Y, OEOy EcuAaIe*EI1/2OEO,SIO OA*EIEy3/4Y1/2SIODAT, OUSIO Ieo, SIODAT *E AeEo SIO2 OAEIEOOONn 0 = Internal clock, 1 = External clock Data direction Tx/Rx selection AIOOAEMSB ECLSB ExIE*EI EcuAaOIe*EI, OUSIODAT OEy3/4Y* EoSIO AUEY (R) 1/2O 0 = MSB mode, 1 = LSB mode OOAE1/4Aae/ oE1/4O 0x00 Clock source select 2 SIO Ey3/4Y1/4AaeAE/ (SIOCON) SIODAT 0x01D14004 R/W SIOEy3/4Y1/4AaeAE/ oE1/4O 0x00 3 SIO IOAEOeAE/1/4Aae ( SBRDR) Baud rate = MCLK / 2 /(Prescaler value + 1) SBRDR 0x01D14008 R/W SIOIOAEOeAE/1/4Aae oE1/4O0x00 SIO 1/4aoAEEyAae/(IVTCNT) 1/4ao Intervals (between 8-bit data) = MCLK / 4/ ( IVTCNT +1) 0x01D1400C R/W SIO1/4ao1/4AEEyAae/ oE1/4O 0x00 DCNTZeIO 1/4AaeAE/ AeEo [1] 0: OEiBDMA1 CoDMA *In Co. *Ine AIEC 0E SIOEOOCe 0 DMAIO|AOEEe oE1/4O 0x00 DCNTZEe 4 IVTCNT 5 OAI1 SIO 1/4aoAEEyAae/(IVTCNT) SIO x/OU DMAAOO|AE1/2 DCNTZ 0x01D14010 R/W SIO dma1/4AEEy0 IAuAE DCNTZ1 BIT 1: OEiBDMA1 DCNTZ0 [0] 0: OEiBDMA0 CoDMA *In 1: OEiBDMA0 Co. *Ine *InCeo AIEC 0E SIOEOOCe *InCeo |
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